/***************************************************************************
 *                      COPYRIGHT NOTICE
 *             Copyright 2019 Horizon Robotics, Inc.
 *                     All rights reserved.
 ***************************************************************************/

#ifndef __HOBOT_SIF_REG_H__
#define __HOBOT_SIF_REG_H__

#include "vio_hw_common_api.h"
#include "hobot_dev_sif.h"

#define SIF_IPI_MAX	13

enum sif_reg {
	SIF_SETTING,
	SIF_SHD_UP_SEL,
	SIF_SHD_UP_RDY,
	SIF_CLK_GATING,
	SIF_SW_RESET,
	SIF_SYS_REPORT,
	SIF_FRM_EN_INT,
	SIF_FRM_INT,
	SIF_DVP_IN_SET,
	SIF_MIPI_RX_SET,
	SIF_DVP_IN_CFG0,
	SIF_MIPI_RX0_CFG0,
	SIF_MIPI_RX0_CFG1,
	SIF_MIPI_RX0_CFG2,
	SIF_MIPI_RX0_CFG3,
	SIF_MIPI_RX1_CFG0,
	SIF_MIPI_RX1_CFG1,
	SIF_MIPI_RX1_CFG2,
	SIF_MIPI_RX1_CFG3,
	SIF_MIPI_RX2_CFG0,
	SIF_MIPI_RX2_CFG1,
	SIF_MIPI_RX3_CFG0,
	SIF_MIPI_RX3_CFG1,
	SIF_FRM_ID_DVP_IN_CFG,
	SIF_FRM_ID_RX0_IPI0_CFG,
	SIF_FRM_ID_RX0_IPI1_CFG,
	SIF_FRM_ID_RX0_IPI2_CFG,
	SIF_FRM_ID_RX0_IPI3_CFG,
	SIF_FRM_ID_RX1_IPI0_CFG,
	SIF_FRM_ID_RX1_IPI1_CFG,
	SIF_FRM_ID_RX1_IPI2_CFG,
	SIF_FRM_ID_RX1_IPI3_CFG,
	SIF_FRM_ID_RX2_IPI0_CFG,
	SIF_FRM_ID_RX2_IPI1_CFG,
	SIF_FRM_ID_RX3_IPI0_CFG,
	SIF_FRM_ID_RX3_IPI1_CFG,
	SIF_VIO_BYPASS_CFG,
	SIF_MUX_OUT_MODE,
	SIF_MUX_OUT_SEL,
	SIF_MULTI_FRAME_INT,
	SIF_MULTI_FRAME_FRM_ID,
	SIF_FRAME_ID_IAR_CFG,
	SIF_ISP_EXP_CFG,
	SIF_VC_GAIN_ISP0,
	SIF_DOL_RX_LINE_SHIFT_MODE0,
	SIF_DOL_RX_LINE_SHIFT_MODE1,
	SIF_DOL_RX_LINE_SHIFT_MODE2,
	SIF_DOL_RX_LINE_SHIFT_MODE3,
	SIF_MOT_DET_MODE,
	SIF_FRAME_ID_IPI_0_1,
	SIF_FRAME_ID_IPI_2_3,
	SIF_FRAME_ID_IPI_4_5,
	SIF_FRAME_ID_IPI_6_7,
	SIF_FRAME_ID_IPI_8_9,
	SIF_FRAME_ID_IPI_10_11,
	SIF_FRAME_ID_DVP_IAR,
	SIF_FRAME_ID_IN_BUF_0_1,
	SIF_FRAME_ID_IN_BUF_2_3,
	SIF_FRAME_ID_IN_BUF_4_5,
	SIF_FRAME_ID_IN_BUF_6_7,
	SIF_TIMESTAMP_MULTI_L,
	SIF_TIMESTAMP_MULTI_M,
	SIF_TIMESTAMP0_LSB,
	SIF_TIMESTAMP0_MSB,
	SIF_TIMESTAMP1_LSB,
	SIF_TIMESTAMP1_MSB,
	SIF_TIMESTAMP2_LSB,
	SIF_TIMESTAMP2_MSB,
	SIF_TIMESTAMP3_LSB,
	SIF_TIMESTAMP3_MSB,
	SIF_TIMESTAMP4_LSB,
	SIF_TIMESTAMP4_MSB,
	SIF_TIMESTAMP5_LSB,
	SIF_TIMESTAMP5_MSB,
	SIF_TIMESTAMP6_LSB,
	SIF_TIMESTAMP6_MSB,
	SIF_TIMESTAMP7_LSB,
	SIF_TIMESTAMP7_MSB,
	SIF_TIMESTAMP_IAR_LSB,
	SIF_TIMESTAMP_IAR_MSB,
	SIF_MIPI_RX_STATUS0,
	SIF_MIPI_RX_STATUS1,
	SIF_MIPI_RX_STATUS2,
	SIF_MIPI_RX_STATUS3,
	SIF_MIPI_RX_STATUS4,
	SIF_MIPI_RX_STATUS5,
	SIF_MIPI_RX_STATUS6,
	SIF_MIPI_RX_STATUS7,
	SIF_MIPI_RX_STATUS8,
	SIF_MIPI_RX_STATUS9,
	SIF_MIPI_RX_STATUS10,
	SIF_MIPI_RX_STATUS11,
	SIF_DVP_IN_STATUS,
	SIF_MIPI_VIO_BYPASS_DEBUG,
	SIF_DEFRM_DBG0,
	SIF_DEFRM_DBG1,
	SIF_DEFRM_DBG2,
	SIF_DEFRM_DBG3,
	SIF_ERR_STATUS,
	SIF_ERR_STATUS_MASK,
	SIF_IN_BUF_OVERFLOW,
	SIF_IN_BUF_OVERFLOW_MASK,
	SIF_OUT_FRM_CTRL,
	SIF_AXI_CTRL_W0,
	SIF_AXI_CTRL_R0,
	SIF_AXI_CTRL_R1,
	SIF_AXI_FRM0_W_ADDR0,
	SIF_AXI_FRM0_W_ADDR1,
	SIF_AXI_FRM0_W_ADDR2,
	SIF_AXI_FRM0_W_ADDR3,
	SIF_AXI_FRM1_W_ADDR0,
	SIF_AXI_FRM1_W_ADDR1,
	SIF_AXI_FRM1_W_ADDR2,
	SIF_AXI_FRM1_W_ADDR3,
	SIF_AXI_FRM2_W_ADDR0,
	SIF_AXI_FRM2_W_ADDR1,
	SIF_AXI_FRM2_W_ADDR2,
	SIF_AXI_FRM2_W_ADDR3,
	SIF_AXI_FRM3_W_ADDR0,
	SIF_AXI_FRM3_W_ADDR1,
	SIF_AXI_FRM3_W_ADDR2,
	SIF_AXI_FRM3_W_ADDR3,
	SIF_AXI_FRM4_W_ADDR0,
	SIF_AXI_FRM4_W_ADDR1,
	SIF_AXI_FRM4_W_ADDR2,
	SIF_AXI_FRM4_W_ADDR3,
	SIF_AXI_FRM5_W_ADDR0,
	SIF_AXI_FRM5_W_ADDR1,
	SIF_AXI_FRM5_W_ADDR2,
	SIF_AXI_FRM5_W_ADDR3,
	SIF_AXI_FRM6_W_ADDR0,
	SIF_AXI_FRM6_W_ADDR1,
	SIF_AXI_FRM6_W_ADDR2,
	SIF_AXI_FRM6_W_ADDR3,
	SIF_AXI_FRM7_W_ADDR0,
	SIF_AXI_FRM7_W_ADDR1,
	SIF_AXI_FRM7_W_ADDR2,
	SIF_AXI_FRM7_W_ADDR3,
	SIF_AXI_FRM0_W_STRIDE,
	SIF_AXI_FRM1_W_STRIDE,
	SIF_AXI_FRM2_W_STRIDE,
	SIF_AXI_FRM3_W_STRIDE,
	SIF_AXI_FRM4_W_STRIDE,
	SIF_AXI_FRM5_W_STRIDE,
	SIF_AXI_FRM6_W_STRIDE,
	SIF_AXI_FRM7_W_STRIDE,
	SIF_AXI_BUF_STATUS,
	SIF_AXI_BUS_OWNER,
	SIF_AXI_BUS_OWNER_RELEASE,
	SIF_AXI_FRM_W_LIMIT_SET,
	SIF_AXI_FRM_W_LIMIT_UP,
	SIF_AXI_FRM_W_LIMIT_BOT,
	SIF_AXI_FRM_W_LIMIT_DET,
	SIF_AXI_FRM_W_LIMIT_LOG,
	SIF_AXI_FRM_W_BUSY_RPT,
	SIF_AXI_FRM_R1_START,
	SIF_AXI_FRM_R2_START,
	SIF_AXI_FRM0_R_ADDR,
	SIF_AXI_FRM1_R_ADDR,
	SIF_AXI_FRM2_R_ADDR,
	SIF_AXI_FRM3_R_ADDR,
	SIF_AXI_FRM4_R_ADDR,
	SIF_AXI_FRM5_R_ADDR,
	SIF_AXI_FRM6_R_ADDR,
	SIF_AXI_FRM7_R_ADDR,
	SIF_AXI_FRM0_R_STRIDE,
	SIF_AXI_FRM1_R_STRIDE,
	SIF_AXI_FRM2_R_STRIDE,
	SIF_AXI_FRM3_R_STRIDE,
	SIF_AXI_FRM4_R_STRIDE,
	SIF_AXI_FRM5_R_STRIDE,
	SIF_AXI_FRM6_R_STRIDE,
	SIF_AXI_FRM7_R_STRIDE,
	SIF_OUT_BUF_CTRL,
	SIF_OUT_BUF_FIFO_SIZE,
	SIF_OUT_BUF_ISP0_CFG,
	SIF_OUT_BUF_ISP1_CFG,
	SIF_ISP_PERFORMANCE,
	SIF_OUT_EN_INT,
	SIF_OUT_INT,
	SIF_PAT_GEN_IPI_EN,
	SIF_PAT_GEN_ENABLE,
	SIF_PAT_GEN0_SIZE,
	SIF_PAT_GEN0_IMG,
	SIF_PAT_GEN0_COL0,
	SIF_PAT_GEN0_COL1,
	SIF_PAT_GEN0_COL2,
	SIF_PAT_GEN0_CFG,
	SIF_PAT_GEN1_SIZE,
	SIF_PAT_GEN1_IMG,
	SIF_PAT_GEN1_COL0,
	SIF_PAT_GEN1_COL1,
	SIF_PAT_GEN1_COL2,
	SIF_PAT_GEN1_CFG,
	SIF_PAT_GEN2_SIZE,
	SIF_PAT_GEN2_IMG,
	SIF_PAT_GEN2_COL0,
	SIF_PAT_GEN2_COL1,
	SIF_PAT_GEN2_COL2,
	SIF_PAT_GEN2_CFG,
	SIF_PAT_GEN3_SIZE,
	SIF_PAT_GEN3_IMG,
	SIF_PAT_GEN3_COL0,
	SIF_PAT_GEN3_COL1,
	SIF_PAT_GEN3_COL2,
	SIF_PAT_GEN3_CFG,
	SIF_PAT_GEN4_SIZE,
	SIF_PAT_GEN4_IMG,
	SIF_PAT_GEN4_COL0,
	SIF_PAT_GEN4_COL1,
	SIF_PAT_GEN4_COL2,
	SIF_PAT_GEN4_CFG,
	SIF_YUV422_TRANS,
	NUM_OF_SIF_REG,
};

static struct vio_reg_def sif_regs[NUM_OF_SIF_REG]={
	{"SIF_SETTING"				   , 0x0000 , RW},
	{"SIF_SHD_UP_SEL"			   , 0x0004 , RW},
	{"SIF_SHD_UP_RDY"			   , 0x0008 , W1T},
	{"SIF_CLK_GATING"			   , 0x000C , RW},
	{"SIF_SW_RESET"				   , 0x0010 , RW},
	{"SIF_SYS_REPORT"			   , 0x0014 , RO},
	{"SIF_FRM_EN_INT"			   , 0x0018 , RW},
	{"SIF_FRM_INT"				   , 0x001C , W1C},
	{"SIF_DVP_IN_SET"			   , 0x0020 , RW},
	{"SIF_MIPI_RX_SET"			   , 0x0024 , RW},
	{"SIF_DVP_IN_CFG0"			   , 0x0028 , RW},
	{"SIF_MIPI_RX0_CFG0" 		   , 0x002C , RW},
	{"SIF_MIPI_RX0_CFG1" 		   , 0x0030 , RW},
	{"SIF_MIPI_RX0_CFG2" 		   , 0x0034 , RW},
	{"SIF_MIPI_RX0_CFG3" 		   , 0x0038 , RW},
	{"SIF_MIPI_RX1_CFG0" 		   , 0x003C , RW},
	{"SIF_MIPI_RX1_CFG1" 		   , 0x0040 , RW},
	{"SIF_MIPI_RX1_CFG2" 		   , 0x0044 , RW},
	{"SIF_MIPI_RX1_CFG3" 		   , 0x0048 , RW},
	{"SIF_MIPI_RX2_CFG0" 		   , 0x004C , RW},
	{"SIF_MIPI_RX2_CFG1" 		   , 0x0050 , RW},
	{"SIF_MIPI_RX3_CFG0" 		   , 0x0054 , RW},
	{"SIF_MIPI_RX3_CFG1" 		   , 0x0058 , RW},
	{"SIF_FRM_ID_DVP_IN_CFG" 	   , 0x005C , RW},
	{"SIF_FRM_ID_RX0_IPI0_CFG"	   , 0x0060 , RW},
	{"SIF_FRM_ID_RX0_IPI1_CFG"	   , 0x0064 , RW},
	{"SIF_FRM_ID_RX0_IPI2_CFG"	   , 0x0068 , RW},
	{"SIF_FRM_ID_RX0_IPI3_CFG"	   , 0x006C , RW},
	{"SIF_FRM_ID_RX1_IPI0_CFG"	   , 0x0070 , RW},
	{"SIF_FRM_ID_RX1_IPI1_CFG"	   , 0x0074 , RW},
	{"SIF_FRM_ID_RX1_IPI2_CFG"	   , 0x0078 , RW},
	{"SIF_FRM_ID_RX1_IPI3_CFG"	   , 0x007C , RW},
	{"SIF_FRM_ID_RX2_IPI0_CFG"	   , 0x0080 , RW},
	{"SIF_FRM_ID_RX2_IPI1_CFG"	   , 0x0084 , RW},
	{"SIF_FRM_ID_RX3_IPI0_CFG"	   , 0x0088 , RW},
	{"SIF_FRM_ID_RX3_IPI1_CFG"	   , 0x008C , RW},
	{"SIF_VIO_BYPASS_CFG"		   , 0x0090 , RW},
	{"SIF_MUX_OUT_MODE"			   , 0x0094 , RW},
	{"SIF_MUX_OUT_SEL"			   , 0x0098 , RW},
	{"SIF_MULTI_FRAME_INT"		   , 0x00A0 , RW},
	{"SIF_MULTI_FRAME_FRM_ID"	   , 0x00A4 , RO},
	{"SIF_FRAME_ID_IAR_CFG"		   , 0x00A8 , RW},
	{"SIF_ISP_EXP_CFG"			   , 0x00B0 , RW},
	{"SIF_VC_GAIN_ISP0"			   , 0x00B4 , RW},
	{"SIF_DOL_RX_LINE_SHIFT_MODE0" , 0x00C0 , RW},
	{"SIF_DOL_RX_LINE_SHIFT_MODE1" , 0x00C4 , RW},
	{"SIF_DOL_RX_LINE_SHIFT_MODE2" , 0x00C8 , RW},
	{"SIF_DOL_RX_LINE_SHIFT_MODE3" , 0x00CC , RW},
	{"SIF_MOT_DET_MODE"			   , 0x00D0 , RW},
	{"SIF_FRAME_ID_IPI_0_1"		   , 0x0100 , RO},
	{"SIF_FRAME_ID_IPI_2_3"		   , 0x0104 , RO},
	{"SIF_FRAME_ID_IPI_4_5"		   , 0x0108 , RO},
	{"SIF_FRAME_ID_IPI_6_7"		   , 0x010C , RO},
	{"SIF_FRAME_ID_IPI_8_9"		   , 0x0110 , RO},
	{"SIF_FRAME_ID_IPI_10_11"	   , 0x0114 , RO},
	{"SIF_FRAME_ID_DVP_IAR"		   , 0x0118 , RO},
	{"SIF_FRAME_ID_IN_BUF_0_1"	   , 0x011C , RO},
	{"SIF_FRAME_ID_IN_BUF_2_3"	   , 0x0120 , RO},
	{"SIF_FRAME_ID_IN_BUF_4_5"	   , 0x0124 , RO},
	{"SIF_FRAME_ID_IN_BUF_6_7"	   , 0x0128 , RO},
	{"SIF_TIMESTAMP_MULTI_L" 	   , 0x0130 , RO},
	{"SIF_TIMESTAMP_MULTI_M" 	   , 0x0134 , RO},
	{"SIF_TIMESTAMP0_LSB"		   , 0x0138 , RO},
	{"SIF_TIMESTAMP0_MSB"		   , 0x013C , RO},
	{"SIF_TIMESTAMP1_LSB"		   , 0x0140 , RO},
	{"SIF_TIMESTAMP1_MSB"		   , 0x0144 , RO},
	{"SIF_TIMESTAMP2_LSB"		   , 0x0148 , RO},
	{"SIF_TIMESTAMP2_MSB"		   , 0x014C , RO},
	{"SIF_TIMESTAMP3_LSB"		   , 0x0150 , RO},
	{"SIF_TIMESTAMP3_MSB"		   , 0x0154 , RO},
	{"SIF_TIMESTAMP4_LSB"		   , 0x0158 , RO},
	{"SIF_TIMESTAMP4_MSB"		   , 0x015C , RO},
	{"SIF_TIMESTAMP5_LSB"		   , 0x0160 , RO},
	{"SIF_TIMESTAMP5_MSB"		   , 0x0164 , RO},
	{"SIF_TIMESTAMP6_LSB"		   , 0x0168 , RO},
	{"SIF_TIMESTAMP6_MSB"		   , 0x016C , RO},
	{"SIF_TIMESTAMP7_LSB"		   , 0x0170 , RO},
	{"SIF_TIMESTAMP7_MSB"		   , 0x0174 , RO},
	{"SIF_TIMESTAMP_IAR_LSB" 	   , 0x0178 , RO},
	{"SIF_TIMESTAMP_IAR_MSB"	   , 0x017C , RO},
	{"SIF_MIPI_RX_STATUS0"		   , 0x0180 , RO},
	{"SIF_MIPI_RX_STATUS1"		   , 0x0184 , RO},
	{"SIF_MIPI_RX_STATUS2"		   , 0x0188 , RO},
	{"SIF_MIPI_RX_STATUS3"		   , 0x018C , RO},
	{"SIF_MIPI_RX_STATUS4"		   , 0x0190 , RO},
	{"SIF_MIPI_RX_STATUS5"		   , 0x0194 , RO},
	{"SIF_MIPI_RX_STATUS6"		   , 0x0198 , RO},
	{"SIF_MIPI_RX_STATUS7"		   , 0x019C , RO},
	{"SIF_MIPI_RX_STATUS8"		   , 0x01A0 , RO},
	{"SIF_MIPI_RX_STATUS9"		   , 0x01A4 , RO},
	{"SIF_MIPI_RX_STATUS10"		   , 0x01A8 , RO},
	{"SIF_MIPI_RX_STATUS11"		   , 0x01AC , RO},
	{"SIF_DVP_IN_STATUS" 		   , 0x01B0 , RO},
	{"SIF_MIPI_VIO_BYPASS_DEBUG"   , 0x01C0 , RO},
	{"SIF_DEFRM_DBG0"			   , 0x01C4 , RO},
	{"SIF_DEFRM_DBG1"			   , 0x01C8 , RO},
	{"SIF_DEFRM_DBG2"			   , 0x01CC , RO},
	{"SIF_DEFRM_DBG3"			   , 0x01D0 , RO},
	{"SIF_ERR_STATUS"			   , 0x01E0 , RO},
	{"SIF_ERR_STATUS_MASK"		   , 0x01E4 , RW},
	{"SIF_IN_BUF_OVERFLOW"		   , 0x01E8 , RO},
	{"SIF_IN_BUF_OVERFLOW_MASK"	   , 0x01EC , RW},
	{"SIF_OUT_FRM_CTRL"			   , 0x0200 , RW},
	{"SIF_AXI_CTRL_W0"			   , 0x0204 , RW},
	{"SIF_AXI_CTRL_R0"			   , 0x0208 , RW},
	{"SIF_AXI_CTRL_R1"			   , 0x020C , RW},
	{"SIF_AXI_FRM0_W_ADDR0"		   , 0x0220 , RW},
	{"SIF_AXI_FRM0_W_ADDR1"		   , 0x0224 , RW},
	{"SIF_AXI_FRM0_W_ADDR2"		   , 0x0228 , RW},
	{"SIF_AXI_FRM0_W_ADDR3"		   , 0x022C , RW},
	{"SIF_AXI_FRM1_W_ADDR0"		   , 0x0230 , RW},
	{"SIF_AXI_FRM1_W_ADDR1"		   , 0x0234 , RW},
	{"SIF_AXI_FRM1_W_ADDR2"		   , 0x0238 , RW},
	{"SIF_AXI_FRM1_W_ADDR3"		   , 0x023C , RW},
	{"SIF_AXI_FRM2_W_ADDR0"		   , 0x0240 , RW},
	{"SIF_AXI_FRM2_W_ADDR1"		   , 0x0244 , RW},
	{"SIF_AXI_FRM2_W_ADDR2"		   , 0x0248 , RW},
	{"SIF_AXI_FRM2_W_ADDR3"		   , 0x024C , RW},
	{"SIF_AXI_FRM3_W_ADDR0"		   , 0x0250 , RW},
	{"SIF_AXI_FRM3_W_ADDR1"		   , 0x0254 , RW},
	{"SIF_AXI_FRM3_W_ADDR2"		   , 0x0258 , RW},
	{"SIF_AXI_FRM3_W_ADDR3"		   , 0x025C , RW},
	{"SIF_AXI_FRM4_W_ADDR0"		   , 0x0260 , RW},
	{"SIF_AXI_FRM4_W_ADDR1"		   , 0x0264 , RW},
	{"SIF_AXI_FRM4_W_ADDR2"		   , 0x0268 , RW},
	{"SIF_AXI_FRM4_W_ADDR3"		   , 0x026C , RW},
	{"SIF_AXI_FRM5_W_ADDR0"		   , 0x0270 , RW},
	{"SIF_AXI_FRM5_W_ADDR1"		   , 0x0274 , RW},
	{"SIF_AXI_FRM5_W_ADDR2"		   , 0x0278 , RW},
	{"SIF_AXI_FRM5_W_ADDR3"		   , 0x027C , RW},
	{"SIF_AXI_FRM6_W_ADDR0"		   , 0x0280 , RW},
	{"SIF_AXI_FRM6_W_ADDR1"		   , 0x0284 , RW},
	{"SIF_AXI_FRM6_W_ADDR2"		   , 0x0288 , RW},
	{"SIF_AXI_FRM6_W_ADDR3"		   , 0x028C , RW},
	{"SIF_AXI_FRM7_W_ADDR0"		   , 0x0290 , RW},
	{"SIF_AXI_FRM7_W_ADDR1"		   , 0x0294 , RW},
	{"SIF_AXI_FRM7_W_ADDR2"		   , 0x0298 , RW},
	{"SIF_AXI_FRM7_W_ADDR3"		   , 0x029C , RW},
	{"SIF_AXI_FRM0_W_STRIDE" 	   , 0x02A0 , RW},
	{"SIF_AXI_FRM1_W_STRIDE" 	   , 0x02A4 , RW},
	{"SIF_AXI_FRM2_W_STRIDE" 	   , 0x02A8 , RW},
	{"SIF_AXI_FRM3_W_STRIDE" 	   , 0x02AC , RW},
	{"SIF_AXI_FRM4_W_STRIDE" 	   , 0x02B0 , RW},
	{"SIF_AXI_FRM5_W_STRIDE" 	   , 0x02B4 , RW},
	{"SIF_AXI_FRM6_W_STRIDE" 	   , 0x02B8 , RW},
	{"SIF_AXI_FRM7_W_STRIDE" 	   , 0x02BC , RW},
	{"SIF_AXI_BUF_STATUS"		   , 0x02C0 , RO},
	{"SIF_AXI_BUS_OWNER" 		   , 0x02D0 , W1S},
	{"SIF_AXI_BUS_OWNER_RELEASE"       , 0x02F0 , W1T},
	{"SIF_AXI_FRM_W_LIMIT_SET"	   , 0x02D4 , RW},
	{"SIF_AXI_FRM_W_LIMIT_UP"	   , 0x02D8 , RW},
	{"SIF_AXI_FRM_W_LIMIT_BOT"	   , 0x02DC , RW},
	{"SIF_AXI_FRM_W_LIMIT_DET"	   , 0x02E0 , RO},
	{"SIF_AXI_FRM_W_LIMIT_LOG"	   , 0x02E4 , RO},
	{"SIF_AXI_FRM_W_BUSY_RPT"	   , 0x02EC , RO},
	{"SIF_AXI_FRM_R1_START"		   , 0x0400 , W1T},
	{"SIF_AXI_FRM_R2_START"		   , 0x0404 , W1T},
	{"SIF_AXI_FRM0_R_ADDR"		   , 0x0410 , RW},
	{"SIF_AXI_FRM1_R_ADDR"		   , 0x0414 , RW},
	{"SIF_AXI_FRM2_R_ADDR"		   , 0x0418 , RW},
	{"SIF_AXI_FRM3_R_ADDR"		   , 0x041C , RW},
	{"SIF_AXI_FRM4_R_ADDR"		   , 0x0420 , RW},
	{"SIF_AXI_FRM5_R_ADDR"		   , 0x0424 , RW},
	{"SIF_AXI_FRM6_R_ADDR"		   , 0x0428 , RW},
	{"SIF_AXI_FRM7_R_ADDR"		   , 0x042C , RW},
	{"SIF_AXI_FRM0_R_STRIDE" 	   , 0x0430 , RW},
	{"SIF_AXI_FRM1_R_STRIDE" 	   , 0x0434 , RW},
	{"SIF_AXI_FRM2_R_STRIDE" 	   , 0x0438 , RW},
	{"SIF_AXI_FRM3_R_STRIDE" 	   , 0x043C , RW},
	{"SIF_AXI_FRM4_R_STRIDE" 	   , 0x0440 , RW},
	{"SIF_AXI_FRM5_R_STRIDE" 	   , 0x0444 , RW},
	{"SIF_AXI_FRM6_R_STRIDE" 	   , 0x0448 , RW},
	{"SIF_AXI_FRM7_R_STRIDE" 	   , 0x044C , RW},
	{"SIF_OUT_BUF_CTRL"			   , 0x0450 , RW},
	{"SIF_OUT_BUF_FIFO_SIZE" 	   , 0x0454 , RW},
	{"SIF_OUT_BUF_ISP0_CFG"		   , 0x0458 , RW},
	{"SIF_OUT_BUF_ISP1_CFG"		   , 0x045C , RW},
	{"SIF_ISP_PERFORMANCE"		   , 0x0460 , RW},
	{"SIF_OUT_EN_INT"			   , 0x0500 , RW},
	{"SIF_OUT_INT"				   , 0x0504 , W1C},
	{"SIF_PAT_GEN_IPI_EN"		   , 0x0550 , RW},
	{"SIF_PAT_GEN_ENABLE"		   , 0x0554 , RW},
	{"SIF_PAT_GEN0_SIZE" 		   , 0x0560 , RW},
	{"SIF_PAT_GEN0_IMG"			   , 0x0564 , RW},
	{"SIF_PAT_GEN0_COL0" 		   , 0x0570 , RW},
	{"SIF_PAT_GEN0_COL1" 		   , 0x0574 , RW},
	{"SIF_PAT_GEN0_COL2" 		   , 0x0578 , RW},
	{"SIF_PAT_GEN0_CFG"			   , 0x057C , RW},
	{"SIF_PAT_GEN1_SIZE" 		   , 0x0580 , RW},
	{"SIF_PAT_GEN1_IMG"			   , 0x0584 , RW},
	{"SIF_PAT_GEN1_COL0" 		   , 0x0590 , RW},
	{"SIF_PAT_GEN1_COL1" 		   , 0x0594 , RW},
	{"SIF_PAT_GEN1_COL2" 		   , 0x0598 , RW},
	{"SIF_PAT_GEN1_CFG"			   , 0x059C , RW},
	{"SIF_PAT_GEN2_SIZE" 		   , 0x05A0 , RW},
	{"SIF_PAT_GEN2_IMG"			   , 0x05A4 , RW},
	{"SIF_PAT_GEN2_COL0" 		   , 0x05B0 , RW},
	{"SIF_PAT_GEN2_COL1" 		   , 0x05B4 , RW},
	{"SIF_PAT_GEN2_COL2" 		   , 0x05B8 , RW},
	{"SIF_PAT_GEN2_CFG"			   , 0x05BC , RW},
	{"SIF_PAT_GEN3_SIZE" 		   , 0x05C0 , RW},
	{"SIF_PAT_GEN3_IMG"			   , 0x05C4 , RW},
	{"SIF_PAT_GEN3_COL0" 		   , 0x05D0 , RW},
	{"SIF_PAT_GEN3_COL1" 		   , 0x05D4 , RW},
	{"SIF_PAT_GEN3_COL2" 		   , 0x05D8 , RW},
	{"SIF_PAT_GEN3_CFG"			   , 0x05DC , RW},
	{"SIF_PAT_GEN4_SIZE" 		   , 0x05E0 , RW},
	{"SIF_PAT_GEN4_IMG"			   , 0x05E4 , RW},
	{"SIF_PAT_GEN4_COL0" 		   , 0x05F0 , RW},
	{"SIF_PAT_GEN4_COL1" 		   , 0x05F4 , RW},
	{"SIF_PAT_GEN4_COL2" 		   , 0x05F8 , RW},
	{"SIF_PAT_GEN4_CFG"			   , 0x05FC , RW},
	{"SIF_YUV422_TRANS"			   , 0x0600 , RW},
};

enum sif_reg_field {
	/* SIF_SETTING */
	SW_SIF_ENABLE,
	SW_DROP_FRAME_ENABLE,
	SW_STATICS_ERR_CLR,
	SW_HSYNC_INV,
	SW_VSYNC_INV,
	SW_SIF_OWNBIT_UNDERRUN_SKIP_FRM_ENABLE,
	SW_SIF_OVERFLOW_SKIP_FRM_ENABLE,
	SW_DROP_INT_SHOW_ENABLE,
	SW_DROP_FRAME,

	/* SIF_SHD_UP_SEL */
	SW_SHADOW_SELECT_ISP0,
	SW_SHADOW_SELECT13,
	SW_SHADOW_SELECT12,
	SW_SHADOW_SELECT11,
	SW_SHADOW_SELECT10,
	SW_SHADOW_SELECT9,
	SW_SHADOW_SELECT8,
	SW_SHADOW_SELECT7,
	SW_SHADOW_SELECT6,
	SW_SHADOW_SELECT5,
	SW_SHADOW_SELECT4,
	SW_SHADOW_SELECT3,
	SW_SHADOW_SELECT2,
	SW_SHADOW_SELECT1,
	SW_SHADOW_SELECT0,

	/* SIF_SHD_UP_RDY */
	SW_SIF_CONFIG_READY_ISP0,
	SW_SIF_CONFIG_READY13,
	SW_SIF_CONFIG_READY12,
	SW_SIF_CONFIG_READY11,
	SW_SIF_CONFIG_READY10,
	SW_SIF_CONFIG_READY9,
	SW_SIF_CONFIG_READY8,
	SW_SIF_CONFIG_READY7,
	SW_SIF_CONFIG_READY6,
	SW_SIF_CONFIG_READY5,
	SW_SIF_CONFIG_READY4,
	SW_SIF_CONFIG_READY3,
	SW_SIF_CONFIG_READY2,
	SW_SIF_CONFIG_READY1,
	SW_SIF_CONFIG_READY0,

	/* SIF_SW_RESET */

	/* SIF_SYS_REPORT */
	SIF_FRAME_DROP_REPORT,

	/* SIF_FRM_EN_INT */
	SW_SIF_MULTI_FRAME_ID_INT_EN,
	SW_SIF_IN_BUF_OVERFLOW_INT_EN,
	SW_SIF_IN_SIZE_MISMATCH_INT_EN,
	SW_SIF_OUT_BUF_TRIG_ERROR_INT_EN,
	SW_SIF_MIPI_TX_IPI3_FE_INT_EN,
	SW_SIF_MIPI_TX_IPI2_FE_INT_EN,
	SW_SIF_MIPI_TX_IPI1_FE_INT_EN,
	SW_SIF_MIPI_TX_IPI0_FE_INT_EN,
	SW_SIF_MIPI_TX_IPI3_FS_INT_EN,
	SW_SIF_MIPI_TX_IPI2_FS_INT_EN,
	SW_SIF_MIPI_TX_IPI1_FS_INT_EN,
	SW_SIF_MIPI_TX_IPI0_FS_INT_EN,
	SW_SIF_FRM7_DONE_INT_EN,
	SW_SIF_FRM6_DONE_INT_EN,
	SW_SIF_FRM5_DONE_INT_EN,
	SW_SIF_FRM4_DONE_INT_EN,
	SW_SIF_FRM3_DONE_INT_EN,
	SW_SIF_FRM2_DONE_INT_EN,
	SW_SIF_FRM1_DONE_INT_EN,
	SW_SIF_FRM0_DONE_INT_EN,
	SW_SIF_MUX7_OUT_FS_INT_EN,
	SW_SIF_MUX6_OUT_FS_INT_EN,
	SW_SIF_MUX5_OUT_FS_INT_EN,
	SW_SIF_MUX4_OUT_FS_INT_EN,
	SW_SIF_MUX3_OUT_FS_INT_EN,
	SW_SIF_MUX2_OUT_FS_INT_EN,
	SW_SIF_MUX1_OUT_FS_INT_EN,
	SW_SIF_MUX0_OUT_FS_INT_EN,

	/* SIF_FRM_INT */
	SW_SIF_MULTI_FRAME_ID_INT,
	SW_SIF_IN_BUF_OVERFLOW_INT,
	SW_SIF_IN_SIZE_MISMATCH_INT,
	SW_SIF_OUT_BUF_TRIG_ERROR_INT,
	SW_SIF_MIPI_TX_IPI3_FE_INT,
	SW_SIF_MIPI_TX_IPI2_FE_INT,
	SW_SIF_MIPI_TX_IPI1_FE_INT,
	SW_SIF_MIPI_TX_IPI0_FE_INT,
	SW_SIF_MIPI_TX_IPI3_FS_INT,
	SW_SIF_MIPI_TX_IPI2_FS_INT,
	SW_SIF_MIPI_TX_IPI1_FS_INT,
	SW_SIF_MIPI_TX_IPI0_FS_INT,
	SW_SIF_FRM7_DONE_INT,
	SW_SIF_FRM6_DONE_INT,
	SW_SIF_FRM5_DONE_INT,
	SW_SIF_FRM4_DONE_INT,
	SW_SIF_FRM3_DONE_INT,
	SW_SIF_FRM2_DONE_INT,
	SW_SIF_FRM1_DONE_INT,
	SW_SIF_FRM0_DONE_INT,
	SW_SIF_MUX7_OUT_FS_INT,
	SW_SIF_MUX6_OUT_FS_INT,
	SW_SIF_MUX5_OUT_FS_INT,
	SW_SIF_MUX4_OUT_FS_INT,
	SW_SIF_MUX3_OUT_FS_INT,
	SW_SIF_MUX2_OUT_FS_INT,
	SW_SIF_MUX1_OUT_FS_INT,
	SW_SIF_MUX0_OUT_FS_INT,

	/* SIF_DVP_IN_SET */
	SW_DVP_IN_PIX_LENGTH,
	SW_DVP_IN_PIC_FORMAT,

	/* SIF_MIPI_RX_SET */
	SW_MIPI_RX3_PIX_LENGTH,
	SW_MIPI_RX3_PIC_FORMAT,
	SW_MIPI_RX2_PIX_LENGTH,
	SW_MIPI_RX2_PIC_FORMAT,
	SW_MIPI_RX1_PIX_LENGTH,
	SW_MIPI_RX1_PIC_FORMAT,
	SW_MIPI_RX0_PIX_LENGTH,
	SW_MIPI_RX0_PIC_FORMAT,

	/* SIF_DVP_IN_CFG0 */
	SW_DVP_IN_ENABLE,
	SW_DVP_IN_HEIGHT,
	SW_DVP_IN_WIDTH,

	/* SIF_MIPI_RX0_CFG[0-3] */
	SW_MIPI_RX0_IPI0_ENABLE,
	SW_MIPI_RX0_IPI0_HEIGHT,
	SW_MIPI_RX0_IPI0_WIDTH,
	SW_MIPI_RX0_IPI1_ENABLE,
	SW_MIPI_RX0_IPI1_HEIGHT,
	SW_MIPI_RX0_IPI1_WIDTH,
	SW_MIPI_RX0_IPI2_ENABLE,
	SW_MIPI_RX0_IPI2_HEIGHT,
	SW_MIPI_RX0_IPI2_WIDTH,
	SW_MIPI_RX0_IPI3_ENABLE,
	SW_MIPI_RX0_IPI3_HEIGHT,
	SW_MIPI_RX0_IPI3_WIDTH,

	/* SIF_MIPI_RX1_CFG[0-3] */
	SW_MIPI_RX1_IPI0_ENABLE,
	SW_MIPI_RX1_IPI0_HEIGHT,
	SW_MIPI_RX1_IPI0_WIDTH,
	SW_MIPI_RX1_IPI1_ENABLE,
	SW_MIPI_RX1_IPI1_HEIGHT,
	SW_MIPI_RX1_IPI1_WIDTH,
	SW_MIPI_RX1_IPI2_ENABLE,
	SW_MIPI_RX1_IPI2_HEIGHT,
	SW_MIPI_RX1_IPI2_WIDTH,
	SW_MIPI_RX1_IPI3_ENABLE,
	SW_MIPI_RX1_IPI3_HEIGHT,
	SW_MIPI_RX1_IPI3_WIDTH,

	/* SIF_MIPI_RX2_CFG[0-1] */
	SW_MIPI_RX2_IPI0_ENABLE,
	SW_MIPI_RX2_IPI0_HEIGHT,
	SW_MIPI_RX2_IPI0_WIDTH,
	SW_MIPI_RX2_IPI1_ENABLE,
	SW_MIPI_RX2_IPI1_HEIGHT,
	SW_MIPI_RX2_IPI1_WIDTH,

	/* SIF_MIPI_RX3_CFG[0-1] */
	SW_MIPI_RX3_IPI0_ENABLE,
	SW_MIPI_RX3_IPI0_HEIGHT,
	SW_MIPI_RX3_IPI0_WIDTH,
	SW_MIPI_RX3_IPI1_ENABLE,
	SW_MIPI_RX3_IPI1_HEIGHT,
	SW_MIPI_RX3_IPI1_WIDTH,

	/* SIF_FRM_ID_DVP_IN_CFG */
	SW_DVP_FRAME_ID_SET_EN,
	SW_DVP_FRAME_ID_ENABLE,
	SW_DVP_FRAME_ID_INIT,

	/* SIF_FRM_ID_RX[0-3]_IPI[0-3]_CFG */
	SW_RX0_IPI0_FRAME_ID_SET_EN,
	SW_RX0_IPI0_FRAME_ID_ENABLE,
	SW_RX0_IPI0_FRAME_ID_INIT,
	SW_RX0_IPI1_FRAME_ID_SET_EN,
	SW_RX0_IPI1_FRAME_ID_ENABLE,
	SW_RX0_IPI1_FRAME_ID_INIT,
	SW_RX0_IPI2_FRAME_ID_SET_EN,
	SW_RX0_IPI2_FRAME_ID_ENABLE,
	SW_RX0_IPI2_FRAME_ID_INIT,
	SW_RX0_IPI3_FRAME_ID_SET_EN,
	SW_RX0_IPI3_FRAME_ID_ENABLE,
	SW_RX0_IPI3_FRAME_ID_INIT,
	SW_RX1_IPI0_FRAME_ID_SET_EN,
	SW_RX1_IPI0_FRAME_ID_ENABLE,
	SW_RX1_IPI0_FRAME_ID_INIT,
	SW_RX1_IPI1_FRAME_ID_SET_EN,
	SW_RX1_IPI1_FRAME_ID_ENABLE,
	SW_RX1_IPI1_FRAME_ID_INIT,
	SW_RX1_IPI2_FRAME_ID_SET_EN,
	SW_RX1_IPI2_FRAME_ID_ENABLE,
	SW_RX1_IPI2_FRAME_ID_INIT,
	SW_RX1_IPI3_FRAME_ID_SET_EN,
	SW_RX1_IPI3_FRAME_ID_ENABLE,
	SW_RX1_IPI3_FRAME_ID_INIT,
	SW_RX2_IPI0_FRAME_ID_SET_EN,
	SW_RX2_IPI0_FRAME_ID_ENABLE,
	SW_RX2_IPI0_FRAME_ID_INIT,
	SW_RX2_IPI1_FRAME_ID_SET_EN,
	SW_RX2_IPI1_FRAME_ID_ENABLE,
	SW_RX2_IPI1_FRAME_ID_INIT,
	SW_RX3_IPI0_FRAME_ID_SET_EN,
	SW_RX3_IPI0_FRAME_ID_ENABLE,
	SW_RX3_IPI0_FRAME_ID_INIT,
	SW_RX3_IPI1_FRAME_ID_SET_EN,
	SW_RX3_IPI1_FRAME_ID_ENABLE,
	SW_RX3_IPI1_FRAME_ID_INIT,

	/* SIF_VIO_BYPASS_CFG */
	SW_MIPI_RX_OUT_TX_VBP_LINE_MASK_ENABLE,
	SW_MIPI_RX_OUT_TX_LINE_INS_ENABLE,
	SW_MIPI_VIO_BYPASS_MUX_SELECT,
	SW_MIPI_VIO_BYPASS_MUX3_ENABLE,
	SW_MIPI_VIO_BYPASS_MUX2_ENABLE,
	SW_MIPI_VIO_BYPASS_MUX1_ENABLE,
	SW_MIPI_VIO_BYPASS_MUX0_ENABLE,

	/* SIF_MUX_OUT_MODE */
	SW_SIF_BUF_CTRL_F0TO3_4LENGTH,
	SW_SIF_BUF_CTRL_F4TO7_4LENGTH,
	SW_SIF_BUF_CTRL_F0TO3_DVP20BIT,
	SW_SIF_BUF_CTRL_F7TO5_2LENGTH,
	SW_SIF_BUF_CTRL_F6TO4_2LENGTH,
	SW_SIF_BUF_CTRL_F3TO1_2LENGTH,
	SW_SIF_BUF_CTRL_F2TO0_2LENGTH,
	SW_SIF_IN_BUF0_ENABLE,
	SW_SIF_IN_BUF1_ENABLE,
	SW_SIF_IN_BUF2_ENABLE,
	SW_SIF_IN_BUF3_ENABLE,
	SW_SIF_IN_BUF4_ENABLE,
	SW_SIF_IN_BUF5_ENABLE,
	SW_SIF_IN_BUF6_ENABLE,
	SW_SIF_IN_BUF7_ENABLE,
	SW_SIF_MUX7_OUT_ENABLE,
	SW_SIF_MUX6_OUT_ENABLE,
	SW_SIF_MUX5_OUT_ENABLE,
	SW_SIF_MUX4_OUT_ENABLE,
	SW_SIF_MUX3_OUT_ENABLE,
	SW_SIF_MUX2_OUT_ENABLE,
	SW_SIF_MUX1_OUT_ENABLE,
	SW_SIF_MUX0_OUT_ENABLE,

	/* SIF_MUX_OUT_SEL */
	SW_SIF_MUX7_OUT_SELECT,
	SW_SIF_MUX6_OUT_SELECT,
	SW_SIF_MUX5_OUT_SELECT,
	SW_SIF_MUX4_OUT_SELECT,
	SW_SIF_MUX3_OUT_SELECT,
	SW_SIF_MUX2_OUT_SELECT,
	SW_SIF_MUX1_OUT_SELECT,
	SW_SIF_MUX0_OUT_SELECT,

	/* SIF_MULTI_FRAME_INT */
	SW_SIF_W_DDR_INT_EARLY_ENABLE,
	SW_SIF_W_DDR_INT_EARLY_LINE,
	SW_SIF_MULTI_FRAME_ID_INT_PERIOD,
	SW_SIF_MULTI_FRAME_ID_INT_MUX_OUT_SELECT,
	SW_SIF_MULTI_FRAME_ID_INT_CLR,
	SW_SIF_MULTI_FRAME_ID_INT_TRIG_SELECT,
	SW_SIF_MULTI_FRAME_ID_INT_ENABLE,

	/* SIF_MULTI_FRAME_FRM_ID */
	SW_SIF_MULTI_FRAME_ID_REPORT,

	/* SIF_FRAME_ID_IAR_CFG */
	SW_SIF_IAR_MIPI_FRAME_ID_SET_EN,
	SW_SIF_IAR_MIPI_FRAME_ID_ENABLE,
	SW_SIF_IAR_MIPI_FRAME_ID_INIT,

	/* SIF_ISP_EXP_CFG */
	SW_SIF_ISP0_DOL_EXP_NUM,
	SW_MIPI_RX3_IDCODE_EXP_NUM,
	SW_MIPI_RX2_IDCODE_EXP_NUM,
	SW_MIPI_RX1_IDCODE_EXP_NUM,
	SW_MIPI_RX0_IDCODE_EXP_NUM,
	SW_RX3_DOL_HDR_MODE,
	SW_RX2_DOL_HDR_MODE,
	SW_RX1_DOL_HDR_MODE,
	SW_RX0_DOL_HDR_MODE,

	/* SIF_VC_GAIN_ISP0 */
	SW_SIF_ISP0_VC_GAIN_S,
	SW_SIF_ISP0_VC_GAIN_M,
	SW_SIF_ISP0_VC_GAIN_L,
	SW_SIF_ISP0_VC_GAIN_VL,

	/* SIF_FRAME_ID_IPI_[0-11] */
	FRAME_ID_RX0_IPI0_REPORT,
	FRAME_ID_RX0_IPI3_REPORT,
	FRAME_ID_RX0_IPI2_REPORT,
	FRAME_ID_RX0_IPI1_REPORT,
	FRAME_ID_RX1_IPI1_REPORT,
	FRAME_ID_RX1_IPI0_REPORT,
	FRAME_ID_RX1_IPI3_REPORT,
	FRAME_ID_RX1_IPI2_REPORT,
	FRAME_ID_RX2_IPI1_REPORT,
	FRAME_ID_RX2_IPI0_REPORT,
	FRAME_ID_RX3_IPI1_REPORT,
	FRAME_ID_RX3_IPI0_REPORT,

	/* SIF_FRAME_ID_DVP_IAR */
	FRAME_ID_IAR_MIPI_REPORT,
	FRAME_ID_DVP_IN_REPORT,

	/* SIF_FRAME_ID_IN_BUF_[0-8]_[0-8] */
	SIF_FRAME1_ID_REPORT,
	SIF_FRAME0_ID_REPORT,
	SIF_FRAME3_ID_REPORT,
	SIF_FRAME2_ID_REPORT,
	SIF_FRAME5_ID_REPORT,
	SIF_FRAME4_ID_REPORT,
	SIF_FRAME7_ID_REPORT,
	SIF_FRAME6_ID_REPORT,

	/* SIF_TIMESTAMP_MULTI_[LM] */
	SIF_TIMESTAMP_LSB_REPORT,
	SIF_TIMESTAMP_MSB_REPORT,

	/* SIF_TIMESTAMP[0-7]_[LM]SB */
	SIF_TIMESTAMP0_LSB_REPORT,
	SIF_TIMESTAMP0_MSB_REPORT,
	SIF_TIMESTAMP1_LSB_REPORT,
	SIF_TIMESTAMP1_MSB_REPORT,
	SIF_TIMESTAMP2_LSB_REPORT,
	SIF_TIMESTAMP2_MSB_REPORT,
	SIF_TIMESTAMP3_LSB_REPORT,
	SIF_TIMESTAMP3_MSB_REPORT,
	SIF_TIMESTAMP4_LSB_REPORT,
	SIF_TIMESTAMP4_MSB_REPORT,
	SIF_TIMESTAMP5_LSB_REPORT,
	SIF_TIMESTAMP5_MSB_REPORT,
	SIF_TIMESTAMP6_LSB_REPORT,
	SIF_TIMESTAMP6_MSB_REPORT,
	SIF_TIMESTAMP7_LSB_REPORT,
	SIF_TIMESTAMP7_MSB_REPORT,

	/* SIF_TIMESTAMP_IAR_[LM]SB */
	SIF_TIMESTAMP_IAR_LSB_REPORT,
	SIF_TIMESTAMP_IAR_MSB_REPORT,

	/* SIF_DOL_RX_LINE_SHIFT_MODE[0-3] */
	SW_MIPI_RX_LINE_SHIFT1,
	SW_MIPI_RX_LINE_SHIFT0,
	SW_MIPI_RX_LINE_SHIFT3,
	SW_MIPI_RX_LINE_SHIFT2,
	SW_MIPI_RX_LINE_SHIFT5,
	SW_MIPI_RX_LINE_SHIFT4,
	SW_MIPI_RX_LINE_SHIFT7,
	SW_MIPI_RX_LINE_SHIFT6,

	/* SIF_MOT_DET_MODE */
	SW_SIF_IPU_MD_IN_SELECT,
	SW_SIF_IPU_MD_ENABLE,
	SW_SIF_ISP_MD_VC_SELECT,
	SW_SIF_ISP_MD_IN_SELECT,
	SW_SIF_ISP_MD_ENABLE,

	/* SIF_ERR_STATUS */
	SW_SIF_DVP_IN_H_ERROR,
	SW_SIF_RX3_IPI1_H_ERROR,
	SW_SIF_RX3_IPI0_H_ERROR,
	SW_SIF_RX2_IPI1_H_ERROR,
	SW_SIF_RX2_IPI0_H_ERROR,
	SW_SIF_RX1_IPI3_H_ERROR,
	SW_SIF_RX1_IPI2_H_ERROR,
	SW_SIF_RX1_IPI1_H_ERROR,
	SW_SIF_RX1_IPI0_H_ERROR,
	SW_SIF_RX0_IPI3_H_ERROR,
	SW_SIF_RX0_IPI2_H_ERROR,
	SW_SIF_RX0_IPI1_H_ERROR,
	SW_SIF_DVP_IN_V_ERROR,
	SW_SIF_RX3_IPI1_V_ERROR,
	SW_SIF_RX3_IPI0_V_ERROR,
	SW_SIF_RX2_IPI1_V_ERROR,
	SW_SIF_RX2_IPI0_V_ERROR,
	SW_SIF_RX1_IPI3_V_ERROR,
	SW_SIF_RX1_IPI2_V_ERROR,
	SW_SIF_RX1_IPI1_V_ERROR,
	SW_SIF_RX1_IPI0_V_ERROR,
	SW_SIF_RX0_IPI3_V_ERROR,
	SW_SIF_RX0_IPI2_V_ERROR,
	SW_SIF_RX0_IPI1_V_ERROR,
	SW_SIF_RX0_IPI0_V_ERROR,

	/* SIF_ERR_STATUS_MASK */
	SW_SIF_DVP_IN_H_ERROR_MASK,
	SW_SIF_RX3_IPI1_H_ERROR_MASK,
	SW_SIF_RX3_IPI0_H_ERROR_MASK,
	SW_SIF_RX2_IPI1_H_ERROR_MASK,
	SW_SIF_RX2_IPI0_H_ERROR_MASK,
	SW_SIF_RX1_IPI3_H_ERROR_MASK,
	SW_SIF_RX1_IPI2_H_ERROR_MASK,
	SW_SIF_RX1_IPI1_H_ERROR_MASK,
	SW_SIF_RX1_IPI0_H_ERROR_MASK,
	SW_SIF_RX0_IPI3_H_ERROR_MASK,
	SW_SIF_RX0_IPI2_H_ERROR_MASK,
	SW_SIF_RX0_IPI1_H_ERROR_MASK,
	SW_SIF_RX0_IPI0_H_ERROR_MASK,
	SW_SIF_DVP_IN_V_ERROR_MASK,
	SW_SIF_RX3_IPI1_V_ERROR_MASK,
	SW_SIF_RX3_IPI0_V_ERROR_MASK,
	SW_SIF_RX2_IPI1_V_ERROR_MASK,
	SW_SIF_RX2_IPI0_V_ERROR_MASK,
	SW_SIF_RX1_IPI3_V_ERROR_MASK,
	SW_SIF_RX1_IPI2_V_ERROR_MASK,
	SW_SIF_RX1_IPI1_V_ERROR_MASK,
	SW_SIF_RX1_IPI0_V_ERROR_MASK,
	SW_SIF_RX0_IPI3_V_ERROR_MASK,
	SW_SIF_RX0_IPI2_V_ERROR_MASK,
	SW_SIF_RX0_IPI1_V_ERROR_MASK,
	SW_SIF_RX0_IPI0_V_ERROR_MASK,

	/* SIF_IN_BUF_OVERFLOW */
	SW_SIF_BUF7_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF6_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF5_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF4_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF3_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF2_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF1_CTRL_OVERFLOW_ERROR,
	SW_SIF_BUF0_CTRL_OVERFLOW_ERROR,

	/* SIF_IN_BUF_OVERFLOW_MASK */
	SW_SIF_BUF7_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF6_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF5_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF4_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF3_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF2_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF1_CTRL_OVERFLOW_ERROR_MASK,
	SW_SIF_BUF0_CTRL_OVERFLOW_ERROR_MASK,

	/* SIF_OUT_FRM_CTRL */
	SW_SIF_OUT_FRM3_R_ENABLE,
	SW_SIF_OUT_FRM2_R_ENABLE,
	SW_SIF_OUT_FRM1_R_ENABLE,
	SW_SIF_OUT_FRM0_R_ENABLE,
	SW_SIF_OUT_FRM7_W_ENABLE,
	SW_SIF_OUT_FRM6_W_ENABLE,
	SW_SIF_OUT_FRM5_W_ENABLE,
	SW_SIF_OUT_FRM4_W_ENABLE,
	SW_SIF_OUT_FRM3_W_ENABLE,
	SW_SIF_OUT_FRM2_W_ENABLE,
	SW_SIF_OUT_FRM1_W_ENABLE,
	SW_SIF_OUT_FRM0_W_ENABLE,

	/* SIF_AXI_CTRL_W0 (Legacy) */
	/* SIF_AXI_CTRL_R0 (Legacy) */
	/* SIF_AXI_CTRL_R1 (Legacy) */

	/* SIF_AXI_FRM[0-7]_W_ADDR[0-3] */
	SW_SIF_OUT_FRM0_W_DDR0_ADDR,
	SW_SIF_OUT_FRM0_W_DDR1_ADDR,
	SW_SIF_OUT_FRM0_W_DDR2_ADDR,
	SW_SIF_OUT_FRM0_W_DDR3_ADDR,
	SW_SIF_OUT_FRM1_W_DDR0_ADDR,
	SW_SIF_OUT_FRM1_W_DDR1_ADDR,
	SW_SIF_OUT_FRM1_W_DDR2_ADDR,
	SW_SIF_OUT_FRM1_W_DDR3_ADDR,
	SW_SIF_OUT_FRM2_W_DDR0_ADDR,
	SW_SIF_OUT_FRM2_W_DDR1_ADDR,
	SW_SIF_OUT_FRM2_W_DDR2_ADDR,
	SW_SIF_OUT_FRM2_W_DDR3_ADDR,
	SW_SIF_OUT_FRM3_W_DDR0_ADDR,
	SW_SIF_OUT_FRM3_W_DDR1_ADDR,
	SW_SIF_OUT_FRM3_W_DDR2_ADDR,
	SW_SIF_OUT_FRM3_W_DDR3_ADDR,
	SW_SIF_OUT_FRM4_W_DDR0_ADDR,
	SW_SIF_OUT_FRM4_W_DDR1_ADDR,
	SW_SIF_OUT_FRM4_W_DDR2_ADDR,
	SW_SIF_OUT_FRM4_W_DDR3_ADDR,
	SW_SIF_OUT_FRM5_W_DDR0_ADDR,
	SW_SIF_OUT_FRM5_W_DDR1_ADDR,
	SW_SIF_OUT_FRM5_W_DDR2_ADDR,
	SW_SIF_OUT_FRM5_W_DDR3_ADDR,
	SW_SIF_OUT_FRM6_W_DDR0_ADDR,
	SW_SIF_OUT_FRM6_W_DDR1_ADDR,
	SW_SIF_OUT_FRM6_W_DDR2_ADDR,
	SW_SIF_OUT_FRM6_W_DDR3_ADDR,
	SW_SIF_OUT_FRM7_W_DDR0_ADDR,
	SW_SIF_OUT_FRM7_W_DDR1_ADDR,
	SW_SIF_OUT_FRM7_W_DDR2_ADDR,
	SW_SIF_OUT_FRM7_W_DDR3_ADDR,

	/* SIF_AXI_FRM[0-7]_W_STRIDE */
	SW_SIF_OUT_FRM0_W_DDR_STRIDE,
	SW_SIF_OUT_FRM1_W_DDR_STRIDE,
	SW_SIF_OUT_FRM2_W_DDR_STRIDE,
	SW_SIF_OUT_FRM3_W_DDR_STRIDE,
	SW_SIF_OUT_FRM4_W_DDR_STRIDE,
	SW_SIF_OUT_FRM5_W_DDR_STRIDE,
	SW_SIF_OUT_FRM6_W_DDR_STRIDE,
	SW_SIF_OUT_FRM7_W_DDR_STRIDE,

	/* SIF_AXI_BUF_STATUS */
	SIF_OUT_FRM7_BUF_IDX_REPORT,
	SIF_OUT_FRM6_BUF_IDX_REPORT,
	SIF_OUT_FRM5_BUF_IDX_REPORT,
	SIF_OUT_FRM4_BUF_IDX_REPORT,
	SIF_OUT_FRM3_BUF_IDX_REPORT,
	SIF_OUT_FRM2_BUF_IDX_REPORT,
	SIF_OUT_FRM1_BUF_IDX_REPORT,
	SIF_OUT_FRM0_BUF_IDX_REPORT,

	/* SIF_AXI_BUS_OWNER */
	SW_SIF_OUT_FRM7_W_DDR3_OWNER,
	SW_SIF_OUT_FRM7_W_DDR2_OWNER,
	SW_SIF_OUT_FRM7_W_DDR1_OWNER,
	SW_SIF_OUT_FRM7_W_DDR0_OWNER,
	SW_SIF_OUT_FRM6_W_DDR3_OWNER,
	SW_SIF_OUT_FRM6_W_DDR2_OWNER,
	SW_SIF_OUT_FRM6_W_DDR1_OWNER,
	SW_SIF_OUT_FRM6_W_DDR0_OWNER,
	SW_SIF_OUT_FRM5_W_DDR3_OWNER,
	SW_SIF_OUT_FRM5_W_DDR2_OWNER,
	SW_SIF_OUT_FRM5_W_DDR1_OWNER,
	SW_SIF_OUT_FRM5_W_DDR0_OWNER,
	SW_SIF_OUT_FRM4_W_DDR3_OWNER,
	SW_SIF_OUT_FRM4_W_DDR2_OWNER,
	SW_SIF_OUT_FRM4_W_DDR1_OWNER,
	SW_SIF_OUT_FRM4_W_DDR0_OWNER,
	SW_SIF_OUT_FRM3_W_DDR3_OWNER,
	SW_SIF_OUT_FRM3_W_DDR2_OWNER,
	SW_SIF_OUT_FRM3_W_DDR1_OWNER,
	SW_SIF_OUT_FRM3_W_DDR0_OWNER,
	SW_SIF_OUT_FRM2_W_DDR3_OWNER,
	SW_SIF_OUT_FRM2_W_DDR2_OWNER,
	SW_SIF_OUT_FRM2_W_DDR1_OWNER,
	SW_SIF_OUT_FRM2_W_DDR0_OWNER,
	SW_SIF_OUT_FRM1_W_DDR3_OWNER,
	SW_SIF_OUT_FRM1_W_DDR2_OWNER,
	SW_SIF_OUT_FRM1_W_DDR1_OWNER,
	SW_SIF_OUT_FRM1_W_DDR0_OWNER,
	SW_SIF_OUT_FRM0_W_DDR3_OWNER,
	SW_SIF_OUT_FRM0_W_DDR2_OWNER,
	SW_SIF_OUT_FRM0_W_DDR1_OWNER,
	SW_SIF_OUT_FRM0_W_DDR0_OWNER,

	/* SIF_AXI_BUS_OWNER_RELEASE */
	SW_SIF_OUT_FRM7_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM7_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM7_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM7_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM6_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM6_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM6_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM6_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM5_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM5_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM5_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM5_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM4_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM4_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM4_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM4_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM3_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM3_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM3_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM3_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM2_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM2_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM2_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM2_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM1_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM1_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM1_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM1_W_DDR0_OWNER_RELEASE,
	SW_SIF_OUT_FRM0_W_DDR3_OWNER_RELEASE,
	SW_SIF_OUT_FRM0_W_DDR2_OWNER_RELEASE,
	SW_SIF_OUT_FRM0_W_DDR1_OWNER_RELEASE,
	SW_SIF_OUT_FRM0_W_DDR0_OWNER_RELEASE,

	/* SIF_AXI_FRM_W_LIMIT_SET */
	SW_SIF_OUT_FRM_W_ADDR_LIMIT_ENABLE,
	/* SIF_AXI_FRM_W_LIMIT_UP */
	SW_SIF_OUT_FRM_W_ADDR_LIMIT_U,
	/* SIF_AXI_FRM_W_LIMIT_BOT */
	SW_SIF_OUT_FRM_W_ADDR_LIMIT_B,
	/* SIF_AXI_FRM_W_LIMIT_DET */
	SW_SIF_OUT_FRM_W_ADDR_LIMIT_DET,
	/* SIF_AXI_FRM_W_LIMIT_LOG */
	SW_SIF_OUT_FRM_W_ADDR_LIMIT_REPORT,

	/* SIF_AXI_FRM_W_BUSY_RPT */
	SW_SIF_OUT_FRM_IDLE_REPORT,

	/* SIF_AXI_FRM_R1_START */
	SW_SIF_ISP0_DDR_START_IRAM,
	SW_SIF_ISP0_DDR_START_AXI,
	/* SIF_AXI_FRM_R2_START */
	SW_SIF_ISP1_DDR_START_IRAM,
	SW_SIF_ISP1_DDR_START_AXI,

	/* SIF_AXI_FRM[0-7]_R_ADDR */
	SW_SIF_OUT_FRM0_R_DDR_ADDR,
	SW_SIF_OUT_FRM1_R_DDR_ADDR,
	SW_SIF_OUT_FRM2_R_DDR_ADDR,
	SW_SIF_OUT_FRM3_R_DDR_ADDR,
	SW_SIF_OUT_FRM4_R_DDR_ADDR,
	SW_SIF_OUT_FRM5_R_DDR_ADDR,
	SW_SIF_OUT_FRM6_R_DDR_ADDR,
	SW_SIF_OUT_FRM7_R_DDR_ADDR,

	/* SIF_AXI_FRM[0-7]_R_STRIDE */
	SW_SIF_OUT_FRM0_R_DDR_STRIDE,
	SW_SIF_OUT_FRM1_R_DDR_STRIDE,
	SW_SIF_OUT_FRM2_R_DDR_STRIDE,
	SW_SIF_OUT_FRM3_R_DDR_STRIDE,
	SW_SIF_OUT_FRM4_R_DDR_STRIDE,
	SW_SIF_OUT_FRM5_R_DDR_STRIDE,
	SW_SIF_OUT_FRM6_R_DDR_STRIDE,
	SW_SIF_OUT_FRM7_R_DDR_STRIDE,

	/* SIF_OUT_BUF_CTRL */
	SW_SIF_ISP0_UV_INTERLEAVING,
	SW_SIF_ISP0_FLYBY_ENABLE,
	SW_SIF_ISP0_YUV_ENABLE,
	SW_SIF_IPU0_OUT_ENABLE,

	/* SIF_OUT_BUF_FIFO_SIZE */
	SW_SIF_ISP1_PIC_FORMAT,
	SW_SIF_ISP0_PIC_FORMAT,

	/* SIF_OUT_BUF_ISP0_CFG */
	SW_SIF_ISP0_PIX_LENGTH,
	SW_SIF_ISP0_HEIGHT,
	SW_SIF_ISP0_WIDTH,

	/* SIF_OUT_BUF_ISP1_CFG */
	SW_SIF_ISP1_PIX_LENGTH,
	SW_SIF_ISP1_HEIGHT,
	SW_SIF_ISP1_WIDTH,

	/* SIF_ISP_PERFORMANCE */
	SW_SIF_ISP_PERFORMANCE,

	/* SIF_OUT_EN_INT */
	SIF_IPU1_OUT_FE_INT_EN,
	SIF_IPU1_OUT_FS_INT_EN,
	SIF_IPU0_OUT_FE_INT_EN,
	SIF_IPU0_OUT_FS_INT_EN,
	SIF_ISP1_OUT_FE_INT_EN,
	SIF_ISP1_OUT_FS_INT_EN,
	SIF_ISP0_OUT_FE_INT_EN,
	SIF_ISP0_OUT_FS_INT_EN,

	/* SIF_OUT_INT */
	SIF_IPU1_OUT_FE_INT,
	SIF_IPU1_OUT_FS_INT,
	SIF_IPU0_OUT_FE_INT,
	SIF_IPU0_OUT_FS_INT,
	SIF_ISP1_OUT_FE_INT,
	SIF_ISP1_OUT_FS_INT,
	SIF_ISP0_OUT_FE_INT,
	SIF_ISP0_OUT_FS_INT,

	/* SIF_PAT_GEN_IPI_EN */
	SW_DVP_IN_PAT_GEN_OUT,
	SW_RX3_IPI1_PAT_GEN_OUT,
	SW_RX3_IPI0_PAT_GEN_OUT,
	SW_RX2_IPI1_PAT_GEN_OUT,
	SW_RX2_IPI0_PAT_GEN_OUT,
	SW_RX1_IPI3_PAT_GEN_OUT,
	SW_RX1_IPI2_PAT_GEN_OUT,
	SW_RX1_IPI1_PAT_GEN_OUT,
	SW_RX1_IPI0_PAT_GEN_OUT,
	SW_RX0_IPI3_PAT_GEN_OUT,
	SW_RX0_IPI2_PAT_GEN_OUT,
	SW_RX0_IPI1_PAT_GEN_OUT,
	SW_RX0_IPI0_PAT_GEN_OUT,

	/* SIF_PAT_GEN[0-3]_* */
	SW_PAT_GEN4_ENABLE,
	SW_PAT_GEN3_ENABLE,
	SW_PAT_GEN2_ENABLE,
	SW_PAT_GEN1_ENABLE,
	SW_PAT_GEN0_ENABLE,
	SW_PAT_GEN0_VTOTAL_LINE,
	SW_PAT_GEN0_HLINE_TIME,
	SW_PAT_GEN0_VACTIVE_LINE,
	SW_PAT_GEN0_HACTIVE_PIX,
	SW_PAT_GEN0_R_VAL,
	SW_PAT_GEN0_G_VAL,
	SW_PAT_GEN0_B_VAL,
	SW_PAT_GEN0_VBP,
	SW_PAT_GEN0_MODE,
	SW_PAT_GEN0_YUV_OUT,
	SW_PAT_GEN1_VTOTAL_LINE,
	SW_PAT_GEN1_HLINE_TIME,
	SW_PAT_GEN1_VACTIVE_LINE,
	SW_PAT_GEN1_HACTIVE_PIX,
	SW_PAT_GEN1_R_VAL,
	SW_PAT_GEN1_G_VAL,
	SW_PAT_GEN1_B_VAL,
	SW_PAT_GEN1_VBP,
	SW_PAT_GEN1_MODE,
	SW_PAT_GEN1_YUV_OUT,
	SW_PAT_GEN2_VTOTAL_LINE,
	SW_PAT_GEN2_HLINE_TIME,
	SW_PAT_GEN2_VACTIVE_LINE,
	SW_PAT_GEN2_HACTIVE_PIX,
	SW_PAT_GEN2_R_VAL,
	SW_PAT_GEN2_G_VAL,
	SW_PAT_GEN2_B_VAL,
	SW_PAT_GEN2_VBP,
	SW_PAT_GEN2_MODE,
	SW_PAT_GEN2_YUV_OUT,
	SW_PAT_GEN3_VTOTAL_LINE,
	SW_PAT_GEN3_HLINE_TIME,
	SW_PAT_GEN3_VACTIVE_LINE,
	SW_PAT_GEN3_HACTIVE_PIX,
	SW_PAT_GEN3_R_VAL,
	SW_PAT_GEN3_G_VAL,
	SW_PAT_GEN3_B_VAL,
	SW_PAT_GEN3_VBP,
	SW_PAT_GEN3_MODE,
	SW_PAT_GEN3_YUV_OUT,
	SW_PAT_GEN4_VTOTAL_LINE,
	SW_PAT_GEN4_HLINE_TIME,
	SW_PAT_GEN4_VACTIVE_LINE,
	SW_PAT_GEN4_HACTIVE_PIX,
	SW_PAT_GEN4_R_VAL,
	SW_PAT_GEN4_G_VAL,
	SW_PAT_GEN4_B_VAL,
	SW_PAT_GEN4_VBP,
	SW_PAT_GEN4_MODE,
	SW_PAT_GEN4_YUV_OUT,

	/* SIF_YUV422_TRANS */
	SW_YUV422TO420SP_MUX67_ENABLE,
	SW_YUV422TO420SP_MUX45_ENABLE,
	SW_YUV422TO420SP_MUX23_ENABLE,
	SW_YUV422TO420SP_MUX01_ENABLE,

	NUM_OF_SIF_FIELD,
};

static struct vio_field_def sif_fields[NUM_OF_SIF_FIELD] = {
	/* SIF_SETTING */
	{SIF_SETTING, SW_SIF_ENABLE                          , 20 , 1 , 0},
	{SIF_SETTING, SW_DROP_FRAME_ENABLE                   , 19 , 1 , 0},
	{SIF_SETTING, SW_STATICS_ERR_CLR                     , 16 , 1 , 0},
	{SIF_SETTING, SW_HSYNC_INV                           , 13 , 1 , 0},
	{SIF_SETTING, SW_VSYNC_INV                           , 12 , 1 , 0},
	{SIF_SETTING, SW_SIF_OWNBIT_UNDERRUN_SKIP_FRM_ENABLE , 9  , 1 , 0},
	{SIF_SETTING, SW_SIF_OVERFLOW_SKIP_FRM_ENABLE        , 8  , 1 , 1},
	{SIF_SETTING, SW_DROP_INT_SHOW_ENABLE                , 1  , 1 , 0},
	{SIF_SETTING, SW_DROP_FRAME                          , 0  , 1 , 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT_ISP0, 16, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT13, 13, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT12, 12, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT11, 11, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT10, 10, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT9, 9, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT8, 8, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT7, 7, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT6, 6, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT5, 5, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT4, 4, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT3, 3, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT2, 2, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT1, 1, 1, 0},
	{SIF_SHD_UP_SEL, SW_SHADOW_SELECT0, 0, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY_ISP0, 16, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY13, 13, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY12, 12, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY11, 11, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY10, 10, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY9, 9, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY8, 8, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY7, 7, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY6, 6, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY5, 5, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY4, 4, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY3, 3, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY2, 2, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY1, 1, 1, 0},
	{SIF_SHD_UP_RDY, SW_SIF_CONFIG_READY0, 0, 1, 0},
	{SIF_SYS_REPORT, SIF_FRAME_DROP_REPORT, 16, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MULTI_FRAME_ID_INT_EN, 31, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_IN_BUF_OVERFLOW_INT_EN, 29, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_IN_SIZE_MISMATCH_INT_EN, 28, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_OUT_BUF_TRIG_ERROR_INT_EN, 27, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI3_FE_INT_EN, 23, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI2_FE_INT_EN, 22, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI1_FE_INT_EN, 21, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI0_FE_INT_EN, 20, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI3_FS_INT_EN, 19, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI2_FS_INT_EN, 18, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI1_FS_INT_EN, 17, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MIPI_TX_IPI0_FS_INT_EN, 16, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM7_DONE_INT_EN, 15, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM6_DONE_INT_EN, 14, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM5_DONE_INT_EN, 13, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM4_DONE_INT_EN, 12, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM3_DONE_INT_EN, 11, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM2_DONE_INT_EN, 10, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM1_DONE_INT_EN, 9, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_FRM0_DONE_INT_EN, 8, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX7_OUT_FS_INT_EN, 7, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX6_OUT_FS_INT_EN, 6, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX5_OUT_FS_INT_EN, 5, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX4_OUT_FS_INT_EN, 4, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX3_OUT_FS_INT_EN, 3, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX2_OUT_FS_INT_EN, 2, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX1_OUT_FS_INT_EN, 1, 1, 0},
	{SIF_FRM_EN_INT, SW_SIF_MUX0_OUT_FS_INT_EN, 0, 1, 0},
	{SIF_FRM_INT, SW_SIF_MULTI_FRAME_ID_INT, 31, 1, 0},
	{SIF_FRM_INT, SW_SIF_IN_BUF_OVERFLOW_INT, 29, 1, 0},
	{SIF_FRM_INT, SW_SIF_IN_SIZE_MISMATCH_INT, 28, 1, 0},
	{SIF_FRM_INT, SW_SIF_OUT_BUF_TRIG_ERROR_INT, 27, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI3_FE_INT, 23, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI2_FE_INT, 22, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI1_FE_INT, 21, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI0_FE_INT, 20, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI3_FS_INT, 19, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI2_FS_INT, 18, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI1_FS_INT, 17, 1, 0},
	{SIF_FRM_INT, SW_SIF_MIPI_TX_IPI0_FS_INT, 16, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM7_DONE_INT, 15, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM6_DONE_INT, 14, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM5_DONE_INT, 13, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM4_DONE_INT, 12, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM3_DONE_INT, 11, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM2_DONE_INT, 10, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM1_DONE_INT, 9, 1, 0},
	{SIF_FRM_INT, SW_SIF_FRM0_DONE_INT, 8, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX7_OUT_FS_INT, 7, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX6_OUT_FS_INT, 6, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX5_OUT_FS_INT, 5, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX4_OUT_FS_INT, 4, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX3_OUT_FS_INT, 3, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX2_OUT_FS_INT, 2, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX1_OUT_FS_INT, 1, 1, 0},
	{SIF_FRM_INT, SW_SIF_MUX0_OUT_FS_INT, 0, 1, 0},
	{SIF_DVP_IN_SET, SW_DVP_IN_PIX_LENGTH, 4, 3, 0},
	{SIF_DVP_IN_SET, SW_DVP_IN_PIC_FORMAT, 0, 4, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX3_PIX_LENGTH, 28, 3, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX3_PIC_FORMAT, 24, 4, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX2_PIX_LENGTH, 20, 3, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX2_PIC_FORMAT, 16, 4, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX1_PIX_LENGTH, 12, 3, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX1_PIC_FORMAT, 8, 4, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX0_PIX_LENGTH, 4, 3, 0},
	{SIF_MIPI_RX_SET, SW_MIPI_RX0_PIC_FORMAT, 0, 4, 0},
	{SIF_DVP_IN_CFG0, SW_DVP_IN_ENABLE, 31, 1 ,0},
	{SIF_DVP_IN_CFG0, SW_DVP_IN_HEIGHT, 16, 13 ,0},
	{SIF_DVP_IN_CFG0, SW_DVP_IN_WIDTH, 0, 13 ,0},
	{SIF_MIPI_RX0_CFG0, SW_MIPI_RX0_IPI0_ENABLE, 31, 1 ,0},
	{SIF_MIPI_RX0_CFG0, SW_MIPI_RX0_IPI0_HEIGHT, 16, 13 ,0},
	{SIF_MIPI_RX0_CFG0, SW_MIPI_RX0_IPI0_WIDTH, 0, 13 ,0},
	{SIF_MIPI_RX0_CFG1, SW_MIPI_RX0_IPI1_ENABLE, 31, 1 ,0},
	{SIF_MIPI_RX0_CFG1, SW_MIPI_RX0_IPI1_HEIGHT, 16, 13 ,0},
	{SIF_MIPI_RX0_CFG1, SW_MIPI_RX0_IPI1_WIDTH, 0, 13 ,0},
	{SIF_MIPI_RX0_CFG2, SW_MIPI_RX0_IPI2_ENABLE, 31, 1 ,0},
	{SIF_MIPI_RX0_CFG2, SW_MIPI_RX0_IPI2_HEIGHT, 16, 13 ,0},
	{SIF_MIPI_RX0_CFG2, SW_MIPI_RX0_IPI2_WIDTH, 0, 13 ,0},
	{SIF_MIPI_RX0_CFG3, SW_MIPI_RX0_IPI3_ENABLE, 31, 1 ,0},
	{SIF_MIPI_RX0_CFG3, SW_MIPI_RX0_IPI3_HEIGHT, 16, 13 ,0},
	{SIF_MIPI_RX0_CFG3, SW_MIPI_RX0_IPI3_WIDTH, 0, 13 ,0},
	{SIF_MIPI_RX1_CFG0, SW_MIPI_RX1_IPI0_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX1_CFG0, SW_MIPI_RX1_IPI0_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX1_CFG0, SW_MIPI_RX1_IPI0_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX1_CFG1, SW_MIPI_RX1_IPI1_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX1_CFG1, SW_MIPI_RX1_IPI1_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX1_CFG1, SW_MIPI_RX1_IPI1_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX1_CFG2, SW_MIPI_RX1_IPI2_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX1_CFG2, SW_MIPI_RX1_IPI2_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX1_CFG2, SW_MIPI_RX1_IPI2_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX1_CFG3, SW_MIPI_RX1_IPI3_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX1_CFG3, SW_MIPI_RX1_IPI3_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX1_CFG3, SW_MIPI_RX1_IPI3_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX2_CFG0, SW_MIPI_RX2_IPI0_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX2_CFG0, SW_MIPI_RX2_IPI0_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX2_CFG0, SW_MIPI_RX2_IPI0_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX2_CFG1, SW_MIPI_RX2_IPI1_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX2_CFG1, SW_MIPI_RX2_IPI1_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX2_CFG1, SW_MIPI_RX2_IPI1_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX3_CFG0, SW_MIPI_RX3_IPI0_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX3_CFG0, SW_MIPI_RX3_IPI0_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX3_CFG0, SW_MIPI_RX3_IPI0_WIDTH, 0, 13, 0},
	{SIF_MIPI_RX3_CFG1, SW_MIPI_RX3_IPI1_ENABLE, 31, 1, 0},
	{SIF_MIPI_RX3_CFG1, SW_MIPI_RX3_IPI1_HEIGHT, 16, 13, 0},
	{SIF_MIPI_RX3_CFG1, SW_MIPI_RX3_IPI1_WIDTH, 0, 13, 0},
	{SIF_FRM_ID_DVP_IN_CFG, SW_DVP_FRAME_ID_SET_EN, 17, 1, 0},
	{SIF_FRM_ID_DVP_IN_CFG, SW_DVP_FRAME_ID_ENABLE, 16, 1, 0},
	{SIF_FRM_ID_DVP_IN_CFG, SW_DVP_FRAME_ID_INIT, 0, 16, 0},
	{SIF_FRM_ID_RX0_IPI0_CFG , SW_RX0_IPI0_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI0_CFG , SW_RX0_IPI0_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI0_CFG , SW_RX0_IPI0_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX0_IPI1_CFG , SW_RX0_IPI1_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI1_CFG , SW_RX0_IPI1_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI1_CFG , SW_RX0_IPI1_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX0_IPI2_CFG , SW_RX0_IPI2_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI2_CFG , SW_RX0_IPI2_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI2_CFG , SW_RX0_IPI2_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX0_IPI3_CFG , SW_RX0_IPI3_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI3_CFG , SW_RX0_IPI3_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX0_IPI3_CFG , SW_RX0_IPI3_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX1_IPI0_CFG , SW_RX1_IPI0_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI0_CFG , SW_RX1_IPI0_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI0_CFG , SW_RX1_IPI0_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX1_IPI1_CFG , SW_RX1_IPI1_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI1_CFG , SW_RX1_IPI1_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI1_CFG , SW_RX1_IPI1_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX1_IPI2_CFG , SW_RX1_IPI2_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI2_CFG , SW_RX1_IPI2_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI2_CFG , SW_RX1_IPI2_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX1_IPI3_CFG , SW_RX1_IPI3_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI3_CFG , SW_RX1_IPI3_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX1_IPI3_CFG , SW_RX1_IPI3_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX2_IPI0_CFG , SW_RX2_IPI0_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX2_IPI0_CFG , SW_RX2_IPI0_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX2_IPI0_CFG , SW_RX2_IPI0_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX2_IPI1_CFG , SW_RX2_IPI1_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX2_IPI1_CFG , SW_RX2_IPI1_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX2_IPI1_CFG , SW_RX2_IPI1_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX3_IPI0_CFG , SW_RX3_IPI0_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX3_IPI0_CFG , SW_RX3_IPI0_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX3_IPI0_CFG , SW_RX3_IPI0_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_FRM_ID_RX3_IPI1_CFG , SW_RX3_IPI1_FRAME_ID_SET_EN , 17 , 1  , 0},
	{SIF_FRM_ID_RX3_IPI1_CFG , SW_RX3_IPI1_FRAME_ID_ENABLE , 16 , 1  , 0},
	{SIF_FRM_ID_RX3_IPI1_CFG , SW_RX3_IPI1_FRAME_ID_INIT   , 0  , 16 , 0},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_RX_OUT_TX_VBP_LINE_MASK_ENABLE, 17, 1, 0},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_RX_OUT_TX_LINE_INS_ENABLE, 16, 1, 1},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_VIO_BYPASS_MUX_SELECT, 8, 3, 0},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_VIO_BYPASS_MUX3_ENABLE, 3, 1, 1},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_VIO_BYPASS_MUX2_ENABLE, 2, 1, 1},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_VIO_BYPASS_MUX1_ENABLE, 1, 1, 1},
	{SIF_VIO_BYPASS_CFG, SW_MIPI_VIO_BYPASS_MUX0_ENABLE, 0, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F0TO3_4LENGTH, 31, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F4TO7_4LENGTH, 30, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F0TO3_DVP20BIT, 28, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F7TO5_2LENGTH, 27, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F6TO4_2LENGTH, 26, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F3TO1_2LENGTH, 25, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_BUF_CTRL_F2TO0_2LENGTH, 24, 1, 0},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF0_ENABLE, 23, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF1_ENABLE, 22, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF2_ENABLE, 21, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF3_ENABLE, 20, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF4_ENABLE, 19, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF5_ENABLE, 18, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF6_ENABLE, 17, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_IN_BUF7_ENABLE, 16, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX7_OUT_ENABLE, 7, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX6_OUT_ENABLE, 6, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX5_OUT_ENABLE, 5, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX4_OUT_ENABLE, 4, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX3_OUT_ENABLE, 3, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX2_OUT_ENABLE, 2, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX1_OUT_ENABLE, 1, 1, 1},
	{SIF_MUX_OUT_MODE, SW_SIF_MUX0_OUT_ENABLE, 0, 1, 1},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX7_OUT_SELECT, 28, 4, 3},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX6_OUT_SELECT, 24, 4, 3},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX5_OUT_SELECT, 20, 4, 2},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX4_OUT_SELECT, 16, 4, 2},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX3_OUT_SELECT, 12, 4, 1},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX2_OUT_SELECT, 8, 4, 1},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX1_OUT_SELECT, 4, 4, 0},
	{SIF_MUX_OUT_SEL, SW_SIF_MUX0_OUT_SELECT, 0, 4, 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_W_DDR_INT_EARLY_ENABLE            , 31 , 1  , 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_W_DDR_INT_EARLY_LINE              , 16 , 13 , 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_MULTI_FRAME_ID_INT_PERIOD         , 8  , 3  , 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_MULTI_FRAME_ID_INT_MUX_OUT_SELECT , 4  , 3  , 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_MULTI_FRAME_ID_INT_CLR            , 2  , 1  , 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_MULTI_FRAME_ID_INT_TRIG_SELECT    , 1  , 1  , 0},
	{SIF_MULTI_FRAME_INT , SW_SIF_MULTI_FRAME_ID_INT_ENABLE         , 0  , 1  , 0},
	{SIF_MULTI_FRAME_FRM_ID, SW_SIF_MULTI_FRAME_ID_REPORT, 0, 16, 0},
	{SIF_FRAME_ID_IAR_CFG, SW_SIF_IAR_MIPI_FRAME_ID_SET_EN, 17, 1, 0},
	{SIF_FRAME_ID_IAR_CFG, SW_SIF_IAR_MIPI_FRAME_ID_ENABLE, 16, 1, 0},
	{SIF_FRAME_ID_IAR_CFG, SW_SIF_IAR_MIPI_FRAME_ID_INIT, 0, 16, 0},
	{SIF_ISP_EXP_CFG, SW_SIF_ISP0_DOL_EXP_NUM, 24, 3, 3},
	{SIF_ISP_EXP_CFG, SW_MIPI_RX3_IDCODE_EXP_NUM, 20, 2, 2},
	{SIF_ISP_EXP_CFG, SW_MIPI_RX2_IDCODE_EXP_NUM, 16, 2, 2},
	{SIF_ISP_EXP_CFG, SW_MIPI_RX1_IDCODE_EXP_NUM, 12, 3, 2},
	{SIF_ISP_EXP_CFG, SW_MIPI_RX0_IDCODE_EXP_NUM,  8, 3, 2},
	{SIF_ISP_EXP_CFG, SW_RX3_DOL_HDR_MODE, 6, 2, 2},
	{SIF_ISP_EXP_CFG, SW_RX2_DOL_HDR_MODE, 4, 2, 2},
	{SIF_ISP_EXP_CFG, SW_RX1_DOL_HDR_MODE, 2, 2, 2},
	{SIF_ISP_EXP_CFG, SW_RX0_DOL_HDR_MODE, 0, 2, 2},
	{SIF_VC_GAIN_ISP0, SW_SIF_ISP0_VC_GAIN_S, 24, 8, 0},
	{SIF_VC_GAIN_ISP0, SW_SIF_ISP0_VC_GAIN_M, 16, 8, 0},
	{SIF_VC_GAIN_ISP0, SW_SIF_ISP0_VC_GAIN_L, 8, 8, 0},
	{SIF_VC_GAIN_ISP0, SW_SIF_ISP0_VC_GAIN_VL, 0, 8, 0},
	{SIF_FRAME_ID_IPI_0_1   , FRAME_ID_RX0_IPI1_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IPI_0_1   , FRAME_ID_RX0_IPI0_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IPI_2_3   , FRAME_ID_RX0_IPI3_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IPI_2_3   , FRAME_ID_RX0_IPI2_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IPI_4_5   , FRAME_ID_RX1_IPI1_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IPI_4_5   , FRAME_ID_RX1_IPI0_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IPI_6_7   , FRAME_ID_RX1_IPI3_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IPI_6_7   , FRAME_ID_RX1_IPI2_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IPI_8_9   , FRAME_ID_RX2_IPI1_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IPI_8_9   , FRAME_ID_RX2_IPI0_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IPI_10_11 , FRAME_ID_RX3_IPI1_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IPI_10_11 , FRAME_ID_RX3_IPI0_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_DVP_IAR , FRAME_ID_IAR_MIPI_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_DVP_IAR , FRAME_ID_DVP_IN_REPORT   , 0  , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_0_1 , SIF_FRAME1_ID_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_0_1 , SIF_FRAME0_ID_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_2_3 , SIF_FRAME3_ID_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_2_3 , SIF_FRAME2_ID_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_4_5 , SIF_FRAME5_ID_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_4_5 , SIF_FRAME4_ID_REPORT , 0  , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_6_7 , SIF_FRAME7_ID_REPORT , 16 , 16 , 0},
	{SIF_FRAME_ID_IN_BUF_6_7 , SIF_FRAME6_ID_REPORT , 0  , 16 , 0},
	{SIF_TIMESTAMP_MULTI_L, SIF_TIMESTAMP_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP_MULTI_M, SIF_TIMESTAMP_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP0_LSB, SIF_TIMESTAMP0_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP0_MSB, SIF_TIMESTAMP0_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP1_LSB, SIF_TIMESTAMP1_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP1_MSB, SIF_TIMESTAMP1_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP2_LSB, SIF_TIMESTAMP2_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP2_MSB, SIF_TIMESTAMP2_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP3_LSB, SIF_TIMESTAMP3_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP3_MSB, SIF_TIMESTAMP3_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP4_LSB, SIF_TIMESTAMP4_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP4_MSB, SIF_TIMESTAMP4_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP5_LSB, SIF_TIMESTAMP5_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP5_MSB, SIF_TIMESTAMP5_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP6_LSB, SIF_TIMESTAMP6_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP6_MSB, SIF_TIMESTAMP6_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP7_LSB, SIF_TIMESTAMP7_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP7_MSB, SIF_TIMESTAMP7_MSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP_IAR_LSB, SIF_TIMESTAMP_IAR_LSB_REPORT, 0, 32, 0},
	{SIF_TIMESTAMP_IAR_MSB, SIF_TIMESTAMP_IAR_MSB_REPORT, 0, 32, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE0, SW_MIPI_RX_LINE_SHIFT1, 16, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE0, SW_MIPI_RX_LINE_SHIFT0, 0, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE1, SW_MIPI_RX_LINE_SHIFT3, 16, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE1, SW_MIPI_RX_LINE_SHIFT2, 0, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE2, SW_MIPI_RX_LINE_SHIFT5, 16, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE2, SW_MIPI_RX_LINE_SHIFT4, 0, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE3, SW_MIPI_RX_LINE_SHIFT7, 16, 16, 0},
	{SIF_DOL_RX_LINE_SHIFT_MODE3, SW_MIPI_RX_LINE_SHIFT6, 0, 16, 0},
	{SIF_MOT_DET_MODE , SW_SIF_IPU_MD_IN_SELECT , 5 , 1 , 0},
	{SIF_MOT_DET_MODE , SW_SIF_IPU_MD_ENABLE    , 4 , 1 , 0},
	{SIF_MOT_DET_MODE , SW_SIF_ISP_MD_VC_SELECT , 2 , 2 , 0},
	{SIF_MOT_DET_MODE , SW_SIF_ISP_MD_IN_SELECT , 1 , 1 , 0},
	{SIF_MOT_DET_MODE , SW_SIF_ISP_MD_ENABLE    , 0 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_DVP_IN_H_ERROR   , 27 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX3_IPI1_H_ERROR , 26 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX3_IPI0_H_ERROR , 25 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX2_IPI1_H_ERROR , 24 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX2_IPI0_H_ERROR , 23 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI3_H_ERROR , 22 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI2_H_ERROR , 21 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI1_H_ERROR , 20 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI0_H_ERROR , 19 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI3_H_ERROR , 18 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI2_H_ERROR , 17 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI1_H_ERROR , 16 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_DVP_IN_V_ERROR   , 12 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX3_IPI1_V_ERROR , 11 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX3_IPI0_V_ERROR , 10 , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX2_IPI1_V_ERROR , 9  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX2_IPI0_V_ERROR , 8  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI3_V_ERROR , 7  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI2_V_ERROR , 6  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI1_V_ERROR , 5  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX1_IPI0_V_ERROR , 4  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI3_V_ERROR , 3  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI2_V_ERROR , 2  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI1_V_ERROR , 1  , 1 , 0},
	{SIF_ERR_STATUS , SW_SIF_RX0_IPI0_V_ERROR , 0  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_DVP_IN_H_ERROR_MASK   , 28 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX3_IPI1_H_ERROR_MASK , 27 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX3_IPI0_H_ERROR_MASK , 26 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX2_IPI1_H_ERROR_MASK , 25 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX2_IPI0_H_ERROR_MASK , 24 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI3_H_ERROR_MASK , 23 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI2_H_ERROR_MASK , 22 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI1_H_ERROR_MASK , 21 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI0_H_ERROR_MASK , 20 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI3_H_ERROR_MASK , 19 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI2_H_ERROR_MASK , 18 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI1_H_ERROR_MASK , 17 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI0_H_ERROR_MASK , 16 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_DVP_IN_V_ERROR_MASK   , 12 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX3_IPI1_V_ERROR_MASK , 11 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX3_IPI0_V_ERROR_MASK , 10 , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX2_IPI1_V_ERROR_MASK , 9  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX2_IPI0_V_ERROR_MASK , 8  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI3_V_ERROR_MASK , 7  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI2_V_ERROR_MASK , 6  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI1_V_ERROR_MASK , 5  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX1_IPI0_V_ERROR_MASK , 4  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI3_V_ERROR_MASK , 3  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI2_V_ERROR_MASK , 2  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI1_V_ERROR_MASK , 1  , 1 , 0},
	{SIF_ERR_STATUS_MASK , SW_SIF_RX0_IPI0_V_ERROR_MASK , 0  , 1 , 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF7_CTRL_OVERFLOW_ERROR, 7, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF6_CTRL_OVERFLOW_ERROR, 6, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF5_CTRL_OVERFLOW_ERROR, 5, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF4_CTRL_OVERFLOW_ERROR, 4, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF3_CTRL_OVERFLOW_ERROR, 3, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF2_CTRL_OVERFLOW_ERROR, 2, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF1_CTRL_OVERFLOW_ERROR, 1, 1, 0},
	{SIF_IN_BUF_OVERFLOW, SW_SIF_BUF0_CTRL_OVERFLOW_ERROR, 0, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF7_CTRL_OVERFLOW_ERROR_MASK, 7, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF6_CTRL_OVERFLOW_ERROR_MASK, 6, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF5_CTRL_OVERFLOW_ERROR_MASK, 5, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF4_CTRL_OVERFLOW_ERROR_MASK, 4, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF3_CTRL_OVERFLOW_ERROR_MASK, 3, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF2_CTRL_OVERFLOW_ERROR_MASK, 2, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF1_CTRL_OVERFLOW_ERROR_MASK, 1, 1, 0},
	{SIF_IN_BUF_OVERFLOW_MASK, SW_SIF_BUF0_CTRL_OVERFLOW_ERROR_MASK, 0, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM3_R_ENABLE, 19, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM2_R_ENABLE, 18, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM1_R_ENABLE, 17, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM0_R_ENABLE, 16, 1, 1},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM7_W_ENABLE, 7, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM6_W_ENABLE, 6, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM5_W_ENABLE, 5, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM4_W_ENABLE, 4, 1, 1},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM3_W_ENABLE, 3, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM2_W_ENABLE, 2, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM1_W_ENABLE, 1, 1, 0},
	{SIF_OUT_FRM_CTRL, SW_SIF_OUT_FRM0_W_ENABLE, 0, 1, 1},
	{SIF_AXI_FRM0_W_ADDR0, SW_SIF_OUT_FRM0_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM0_W_ADDR1, SW_SIF_OUT_FRM0_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM0_W_ADDR2, SW_SIF_OUT_FRM0_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM0_W_ADDR3, SW_SIF_OUT_FRM0_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM1_W_ADDR0, SW_SIF_OUT_FRM1_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM1_W_ADDR1, SW_SIF_OUT_FRM1_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM1_W_ADDR2, SW_SIF_OUT_FRM1_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM1_W_ADDR3, SW_SIF_OUT_FRM1_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM2_W_ADDR0, SW_SIF_OUT_FRM2_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM2_W_ADDR1, SW_SIF_OUT_FRM2_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM2_W_ADDR2, SW_SIF_OUT_FRM2_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM2_W_ADDR3, SW_SIF_OUT_FRM2_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM3_W_ADDR0, SW_SIF_OUT_FRM3_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM3_W_ADDR1, SW_SIF_OUT_FRM3_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM3_W_ADDR2, SW_SIF_OUT_FRM3_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM3_W_ADDR3, SW_SIF_OUT_FRM3_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM4_W_ADDR0, SW_SIF_OUT_FRM4_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM4_W_ADDR1, SW_SIF_OUT_FRM4_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM4_W_ADDR2, SW_SIF_OUT_FRM4_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM4_W_ADDR3, SW_SIF_OUT_FRM4_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM5_W_ADDR0, SW_SIF_OUT_FRM5_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM5_W_ADDR1, SW_SIF_OUT_FRM5_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM5_W_ADDR2, SW_SIF_OUT_FRM5_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM5_W_ADDR3, SW_SIF_OUT_FRM5_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM6_W_ADDR0, SW_SIF_OUT_FRM6_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM6_W_ADDR1, SW_SIF_OUT_FRM6_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM6_W_ADDR2, SW_SIF_OUT_FRM6_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM6_W_ADDR3, SW_SIF_OUT_FRM6_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM7_W_ADDR0, SW_SIF_OUT_FRM7_W_DDR0_ADDR, 4, 28, 0},
	{SIF_AXI_FRM7_W_ADDR1, SW_SIF_OUT_FRM7_W_DDR1_ADDR, 4, 28, 0},
	{SIF_AXI_FRM7_W_ADDR2, SW_SIF_OUT_FRM7_W_DDR2_ADDR, 4, 28, 0},
	{SIF_AXI_FRM7_W_ADDR3, SW_SIF_OUT_FRM7_W_DDR3_ADDR, 4, 28, 0},
	{SIF_AXI_FRM0_W_STRIDE, SW_SIF_OUT_FRM0_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM1_W_STRIDE, SW_SIF_OUT_FRM1_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM2_W_STRIDE, SW_SIF_OUT_FRM2_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM3_W_STRIDE, SW_SIF_OUT_FRM3_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM4_W_STRIDE, SW_SIF_OUT_FRM4_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM5_W_STRIDE, SW_SIF_OUT_FRM5_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM6_W_STRIDE, SW_SIF_OUT_FRM6_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM7_W_STRIDE, SW_SIF_OUT_FRM7_W_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM7_BUF_IDX_REPORT, 14, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM6_BUF_IDX_REPORT, 12, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM5_BUF_IDX_REPORT, 10, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM4_BUF_IDX_REPORT, 8, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM3_BUF_IDX_REPORT, 6, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM2_BUF_IDX_REPORT, 4, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM1_BUF_IDX_REPORT, 2, 2, 0},
	{SIF_AXI_BUF_STATUS, SIF_OUT_FRM0_BUF_IDX_REPORT, 0, 2, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM7_W_DDR3_OWNER, 31, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM7_W_DDR2_OWNER, 30, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM7_W_DDR1_OWNER, 29, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM7_W_DDR0_OWNER, 28, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM6_W_DDR3_OWNER, 27, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM6_W_DDR2_OWNER, 26, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM6_W_DDR1_OWNER, 25, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM6_W_DDR0_OWNER, 24, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM5_W_DDR3_OWNER, 23, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM5_W_DDR2_OWNER, 22, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM5_W_DDR1_OWNER, 21, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM5_W_DDR0_OWNER, 20, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM4_W_DDR3_OWNER, 19, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM4_W_DDR2_OWNER, 18, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM4_W_DDR1_OWNER, 17, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM4_W_DDR0_OWNER, 16, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM3_W_DDR3_OWNER, 15, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM3_W_DDR2_OWNER, 14, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM3_W_DDR1_OWNER, 13, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM3_W_DDR0_OWNER, 12, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM2_W_DDR3_OWNER, 11, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM2_W_DDR2_OWNER, 10, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM2_W_DDR1_OWNER, 9, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM2_W_DDR0_OWNER, 8, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM1_W_DDR3_OWNER, 7, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM1_W_DDR2_OWNER, 6, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM1_W_DDR1_OWNER, 5, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM1_W_DDR0_OWNER, 4, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM0_W_DDR3_OWNER, 3, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM0_W_DDR2_OWNER, 2, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM0_W_DDR1_OWNER, 1, 1, 0},
	{SIF_AXI_BUS_OWNER, SW_SIF_OUT_FRM0_W_DDR0_OWNER, 0, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM7_W_DDR3_OWNER_RELEASE, 31, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM7_W_DDR2_OWNER_RELEASE, 30, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM7_W_DDR1_OWNER_RELEASE, 29, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM7_W_DDR0_OWNER_RELEASE, 28, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM6_W_DDR3_OWNER_RELEASE, 27, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM6_W_DDR2_OWNER_RELEASE, 26, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM6_W_DDR1_OWNER_RELEASE, 25, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM6_W_DDR0_OWNER_RELEASE, 24, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM5_W_DDR3_OWNER_RELEASE, 23, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM5_W_DDR2_OWNER_RELEASE, 22, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM5_W_DDR1_OWNER_RELEASE, 21, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM5_W_DDR0_OWNER_RELEASE, 20, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM4_W_DDR3_OWNER_RELEASE, 19, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM4_W_DDR2_OWNER_RELEASE, 18, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM4_W_DDR1_OWNER_RELEASE, 17, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM4_W_DDR0_OWNER_RELEASE, 16, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM3_W_DDR3_OWNER_RELEASE, 15, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM3_W_DDR2_OWNER_RELEASE, 14, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM3_W_DDR1_OWNER_RELEASE, 13, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM3_W_DDR0_OWNER_RELEASE, 12, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM2_W_DDR3_OWNER_RELEASE, 11, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM2_W_DDR2_OWNER_RELEASE, 10, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM2_W_DDR1_OWNER_RELEASE, 9, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM2_W_DDR0_OWNER_RELEASE, 8, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM1_W_DDR3_OWNER_RELEASE, 7, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM1_W_DDR2_OWNER_RELEASE, 6, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM1_W_DDR1_OWNER_RELEASE, 5, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM1_W_DDR0_OWNER_RELEASE, 4, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM0_W_DDR3_OWNER_RELEASE, 3, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM0_W_DDR2_OWNER_RELEASE, 2, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM0_W_DDR1_OWNER_RELEASE, 1, 1, 0},
	{SIF_AXI_BUS_OWNER_RELEASE, SW_SIF_OUT_FRM0_W_DDR0_OWNER_RELEASE, 0, 1, 0},
	{SIF_AXI_FRM_W_LIMIT_SET, SW_SIF_OUT_FRM_W_ADDR_LIMIT_ENABLE, 0, 1, 0},
	{SIF_AXI_FRM_W_LIMIT_UP, SW_SIF_OUT_FRM_W_ADDR_LIMIT_U, 0, 32, 0xFFFFFFFF},
	{SIF_AXI_FRM_W_LIMIT_BOT, SW_SIF_OUT_FRM_W_ADDR_LIMIT_B, 0, 32, 0},
	{SIF_AXI_FRM_W_LIMIT_DET, SW_SIF_OUT_FRM_W_ADDR_LIMIT_DET, 0, 1, 0},
	{SIF_AXI_FRM_W_LIMIT_LOG, SW_SIF_OUT_FRM_W_ADDR_LIMIT_REPORT, 0, 32, 0xFFFFFFFF},
	{SIF_AXI_FRM_W_BUSY_RPT, SW_SIF_OUT_FRM_IDLE_REPORT, 16, 1, 0},
	{SIF_AXI_FRM_R1_START, SW_SIF_ISP0_DDR_START_IRAM, 16, 1, 0},
	{SIF_AXI_FRM_R1_START, SW_SIF_ISP0_DDR_START_AXI, 0, 1, 0},
	{SIF_AXI_FRM_R2_START, SW_SIF_ISP1_DDR_START_IRAM, 16, 1, 0},
	{SIF_AXI_FRM_R2_START, SW_SIF_ISP1_DDR_START_AXI, 0, 1, 0},
	{SIF_AXI_FRM0_R_ADDR, SW_SIF_OUT_FRM0_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM1_R_ADDR, SW_SIF_OUT_FRM1_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM2_R_ADDR, SW_SIF_OUT_FRM2_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM3_R_ADDR, SW_SIF_OUT_FRM3_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM4_R_ADDR, SW_SIF_OUT_FRM4_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM5_R_ADDR, SW_SIF_OUT_FRM5_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM6_R_ADDR, SW_SIF_OUT_FRM6_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM7_R_ADDR, SW_SIF_OUT_FRM7_R_DDR_ADDR, 4, 28, 0},
	{SIF_AXI_FRM0_R_STRIDE, SW_SIF_OUT_FRM0_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM1_R_STRIDE, SW_SIF_OUT_FRM1_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM2_R_STRIDE, SW_SIF_OUT_FRM2_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM3_R_STRIDE, SW_SIF_OUT_FRM3_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM4_R_STRIDE, SW_SIF_OUT_FRM4_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM5_R_STRIDE, SW_SIF_OUT_FRM5_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM6_R_STRIDE, SW_SIF_OUT_FRM6_R_DDR_STRIDE, 0, 32, 0},
	{SIF_AXI_FRM7_R_STRIDE, SW_SIF_OUT_FRM7_R_DDR_STRIDE, 0, 32, 0},
	{SIF_OUT_BUF_CTRL, SW_SIF_ISP0_UV_INTERLEAVING, 3, 1, 0},
	{SIF_OUT_BUF_CTRL, SW_SIF_ISP0_FLYBY_ENABLE, 2, 1, 0},
	{SIF_OUT_BUF_CTRL, SW_SIF_ISP0_YUV_ENABLE, 1, 1, 0},
	{SIF_OUT_BUF_CTRL, SW_SIF_IPU0_OUT_ENABLE, 0, 1, 0},
	{SIF_OUT_BUF_FIFO_SIZE, SW_SIF_ISP1_PIC_FORMAT, 28, 4, 0},
	{SIF_OUT_BUF_FIFO_SIZE, SW_SIF_ISP0_PIC_FORMAT, 12, 4, 0},
	{SIF_OUT_BUF_ISP0_CFG, SW_SIF_ISP0_PIX_LENGTH, 29, 3, 0},
	{SIF_OUT_BUF_ISP0_CFG, SW_SIF_ISP0_HEIGHT, 16, 13, 0},
	{SIF_OUT_BUF_ISP0_CFG, SW_SIF_ISP0_WIDTH, 0, 13, 0},
	{SIF_OUT_BUF_ISP1_CFG, SW_SIF_ISP1_PIX_LENGTH, 29, 3, 0},
	{SIF_OUT_BUF_ISP1_CFG, SW_SIF_ISP1_HEIGHT, 16, 13, 0},
	{SIF_OUT_BUF_ISP1_CFG, SW_SIF_ISP1_WIDTH, 0, 13, 0},
	{SIF_ISP_PERFORMANCE, SW_SIF_ISP_PERFORMANCE, 0, 8 , 0},
	{SIF_OUT_EN_INT, SIF_IPU1_OUT_FE_INT_EN, 7, 1, 0},
	{SIF_OUT_EN_INT, SIF_IPU1_OUT_FS_INT_EN, 6, 1, 0},
	{SIF_OUT_EN_INT, SIF_IPU0_OUT_FE_INT_EN, 5, 1, 0},
	{SIF_OUT_EN_INT, SIF_IPU0_OUT_FS_INT_EN, 4, 1, 0},
	{SIF_OUT_EN_INT, SIF_ISP1_OUT_FE_INT_EN, 3, 1, 0},
	{SIF_OUT_EN_INT, SIF_ISP1_OUT_FS_INT_EN, 2, 1, 0},
	{SIF_OUT_EN_INT, SIF_ISP0_OUT_FE_INT_EN, 1, 1, 0},
	{SIF_OUT_EN_INT, SIF_ISP0_OUT_FS_INT_EN, 0, 1, 0},
	{SIF_OUT_INT, SIF_IPU1_OUT_FE_INT, 7, 1, 0},
	{SIF_OUT_INT, SIF_IPU1_OUT_FS_INT, 6, 1, 0},
	{SIF_OUT_INT, SIF_IPU0_OUT_FE_INT, 5, 1, 0},
	{SIF_OUT_INT, SIF_IPU0_OUT_FS_INT, 4, 1, 0},
	{SIF_OUT_INT, SIF_ISP1_OUT_FE_INT, 3, 1, 0},
	{SIF_OUT_INT, SIF_ISP1_OUT_FS_INT, 2, 1, 0},
	{SIF_OUT_INT, SIF_ISP0_OUT_FE_INT, 1, 1, 0},
	{SIF_OUT_INT, SIF_ISP0_OUT_FS_INT, 0, 1, 0},
	{SIF_PAT_GEN_IPI_EN , SW_DVP_IN_PAT_GEN_OUT   , 16 , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX3_IPI1_PAT_GEN_OUT , 11 , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX3_IPI0_PAT_GEN_OUT , 10 , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX2_IPI1_PAT_GEN_OUT , 9  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX2_IPI0_PAT_GEN_OUT , 8  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX1_IPI3_PAT_GEN_OUT , 7  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX1_IPI2_PAT_GEN_OUT , 6  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX1_IPI1_PAT_GEN_OUT , 5  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX1_IPI0_PAT_GEN_OUT , 4  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX0_IPI3_PAT_GEN_OUT , 3  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX0_IPI2_PAT_GEN_OUT , 2  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX0_IPI1_PAT_GEN_OUT , 1  , 1 , 0},
	{SIF_PAT_GEN_IPI_EN , SW_RX0_IPI0_PAT_GEN_OUT , 0  , 1 , 0},
	{SIF_PAT_GEN_ENABLE  , SW_PAT_GEN4_ENABLE       , 4  , 1  , 0},
	{SIF_PAT_GEN_ENABLE  , SW_PAT_GEN3_ENABLE       , 3  , 1  , 0},
	{SIF_PAT_GEN_ENABLE  , SW_PAT_GEN2_ENABLE       , 2  , 1  , 0},
	{SIF_PAT_GEN_ENABLE  , SW_PAT_GEN1_ENABLE       , 1  , 1  , 0},
	{SIF_PAT_GEN_ENABLE  , SW_PAT_GEN0_ENABLE       , 0  , 1  , 0},
	{SIF_PAT_GEN0_SIZE , SW_PAT_GEN0_VTOTAL_LINE  , 16 , 16 , 0},
	{SIF_PAT_GEN0_SIZE , SW_PAT_GEN0_HLINE_TIME   , 0  , 16 , 0},
	{SIF_PAT_GEN0_IMG  , SW_PAT_GEN0_VACTIVE_LINE , 16 , 13 , 0},
	{SIF_PAT_GEN0_IMG  , SW_PAT_GEN0_HACTIVE_PIX  , 0  , 13 , 0},
	{SIF_PAT_GEN0_COL0 , SW_PAT_GEN0_R_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN0_COL1 , SW_PAT_GEN0_G_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN0_COL2 , SW_PAT_GEN0_B_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN0_CFG  , SW_PAT_GEN0_VBP          , 16 , 13 , 0},
	{SIF_PAT_GEN0_CFG  , SW_PAT_GEN0_MODE         , 8  , 3  , 0},
	{SIF_PAT_GEN0_CFG  , SW_PAT_GEN0_YUV_OUT      , 4  , 1  , 0},
	{SIF_PAT_GEN1_SIZE , SW_PAT_GEN1_VTOTAL_LINE  , 16 , 16 , 0},
	{SIF_PAT_GEN1_SIZE , SW_PAT_GEN1_HLINE_TIME   , 0  , 16 , 0},
	{SIF_PAT_GEN1_IMG  , SW_PAT_GEN1_VACTIVE_LINE , 16 , 13 , 0},
	{SIF_PAT_GEN1_IMG  , SW_PAT_GEN1_HACTIVE_PIX  , 0  , 13 , 0},
	{SIF_PAT_GEN1_COL0 , SW_PAT_GEN1_R_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN1_COL1 , SW_PAT_GEN1_G_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN1_COL2 , SW_PAT_GEN1_B_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN1_CFG  , SW_PAT_GEN1_VBP          , 16 , 13 , 0},
	{SIF_PAT_GEN1_CFG  , SW_PAT_GEN1_MODE         , 8  , 3  , 0},
	{SIF_PAT_GEN1_CFG  , SW_PAT_GEN1_YUV_OUT      , 4  , 1  , 0},
	{SIF_PAT_GEN2_SIZE , SW_PAT_GEN2_VTOTAL_LINE  , 16 , 16 , 0},
	{SIF_PAT_GEN2_SIZE , SW_PAT_GEN2_HLINE_TIME   , 0  , 16 , 0},
	{SIF_PAT_GEN2_IMG  , SW_PAT_GEN2_VACTIVE_LINE , 16 , 13 , 0},
	{SIF_PAT_GEN2_IMG  , SW_PAT_GEN2_HACTIVE_PIX  , 0  , 13 , 0},
	{SIF_PAT_GEN2_COL0 , SW_PAT_GEN2_R_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN2_COL1 , SW_PAT_GEN2_G_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN2_COL2 , SW_PAT_GEN2_B_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN2_CFG  , SW_PAT_GEN2_VBP          , 16 , 13 , 0},
	{SIF_PAT_GEN2_CFG  , SW_PAT_GEN2_MODE         , 8  , 3  , 0},
	{SIF_PAT_GEN2_CFG  , SW_PAT_GEN2_YUV_OUT      , 4  , 1  , 0},
	{SIF_PAT_GEN3_SIZE , SW_PAT_GEN3_VTOTAL_LINE  , 16 , 16 , 0},
	{SIF_PAT_GEN3_SIZE , SW_PAT_GEN3_HLINE_TIME   , 0  , 16 , 0},
	{SIF_PAT_GEN3_IMG  , SW_PAT_GEN3_VACTIVE_LINE , 16 , 13 , 0},
	{SIF_PAT_GEN3_IMG  , SW_PAT_GEN3_HACTIVE_PIX  , 0  , 13 , 0},
	{SIF_PAT_GEN3_COL0 , SW_PAT_GEN3_R_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN3_COL1 , SW_PAT_GEN3_G_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN3_COL2 , SW_PAT_GEN3_B_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN3_CFG  , SW_PAT_GEN3_VBP          , 16 , 13 , 0},
	{SIF_PAT_GEN3_CFG  , SW_PAT_GEN3_MODE         , 8  , 3  , 0},
	{SIF_PAT_GEN3_CFG  , SW_PAT_GEN3_YUV_OUT      , 4  , 1  , 0},
	{SIF_PAT_GEN4_SIZE , SW_PAT_GEN4_VTOTAL_LINE  , 16 , 16 , 0},
	{SIF_PAT_GEN4_SIZE , SW_PAT_GEN4_HLINE_TIME   , 0  , 16 , 0},
	{SIF_PAT_GEN4_IMG  , SW_PAT_GEN4_VACTIVE_LINE , 16 , 13 , 0},
	{SIF_PAT_GEN4_IMG  , SW_PAT_GEN4_HACTIVE_PIX  , 0  , 13 , 0},
	{SIF_PAT_GEN4_COL0 , SW_PAT_GEN4_R_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN4_COL1 , SW_PAT_GEN4_G_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN4_COL2 , SW_PAT_GEN4_B_VAL        , 0  , 20 , 0},
	{SIF_PAT_GEN4_CFG  , SW_PAT_GEN4_VBP          , 16 , 13 , 0},
	{SIF_PAT_GEN4_CFG  , SW_PAT_GEN4_MODE         , 8  , 3  , 0},
	{SIF_PAT_GEN4_CFG  , SW_PAT_GEN4_YUV_OUT      , 4  , 1  , 0},
	{SIF_YUV422_TRANS , SW_YUV422TO420SP_MUX67_ENABLE  , 3 , 1 , 0},
	{SIF_YUV422_TRANS , SW_YUV422TO420SP_MUX45_ENABLE  , 2 , 1 , 0},
	{SIF_YUV422_TRANS , SW_YUV422TO420SP_MUX23_ENABLE  , 1 , 1 , 0},
	{SIF_YUV422_TRANS , SW_YUV422TO420SP_MUX01_ENABLE  , 0 , 1 , 0},
};

#endif/*__HOBOT_SIF_REG_H__*/
